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HD74HC74 参数 Datasheet PDF下载

HD74HC74图片预览
型号: HD74HC74
PDF下载: 下载PDF文件 查看货源
内容描述: 双D型触发器(带预置和清除) [Dual D-type Flip-Flops (with Preset and Clear)]
分类和应用: 触发器
文件页数/大小: 8 页 / 108 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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HD74HC74
Dual D-type Flip-Flops (with Preset and Clear)
REJ03D0549-0200
(Previous ADE-205-421)
Rev.2.00
Oct 06, 2005
Description
The flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at the
data input is transferred to the output during the positive going transition to the clock pulse. Preset and clear are
independent of the clock and accomplished by a low level at the appropriate input.
Features
High Speed Operation: t
pd
(Clock to Q or Q) = 14 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1
µA
max
Low Quiescent Supply Current: I
CC
(static) = 2
µA
max (Ta = 25°C)
Ordering Information
Part Name
HD74HC74P
HD74HC74FPEL
HD74HC74TELL
Package Type
DILP-14 pin
SOP-14 pin (JEITA)
TSSOP-14 pin
Package Code
(Previous Code)
PRDP0014AB-B
(DP-14AV)
PRSP0014DF-B
(FP-14DAV)
PTSP0014JA-B
(TTP-14DV)
Package
Abbreviation
P
FP
T
EL (2,000 pcs/reel)
ELL (2,000 pcs/reel)
Taping Abbreviation
(Quantity)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
Preset
L
H
L
H
H
H
H
H
Clear
H
L
L
H
H
H
H
H
L
H
Clock
X
X
X
Data
X
X
X
H
L
X
X
X
Q
H
L
H
*1
Outputs
Q
L
H
H
*1
H
L
No change
No change
No change
L
H
H:
High level
L:
Low level
X:
Irrelevant
Note: 1. Q and
Q
will remain High as long as Preset and Clear are Low, but Q and
Q
are unpredictable, if Preset and
Clear go High simultaneously.
Rev.2.00, Oct 06, 2005 page 1 of 7