HD74HC564, HD74HC574
Octal D-type Flip-Flops (with 3-state outputs)
REJ03D0630-0200
(Previous ADE-205-510)
Rev.2.00
Mar 30, 2006
Description
These devices are positive edge triggered flip-flops. The difference between HD74HC564 and HD74HC574 is only
that the former has inverting outputs and the latter has noninvertering outputs.
Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q or
Q
outputs on positive
going transitions of the clock (CK) input. When a high logic level is applied to the output control (OC) input, all
outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the
storage elements.
Features
•
High Speed Operation: t
pd
(Clock to Output) = 13 ns typ (C
L
= 50 pF)
•
High Output Current: Fanout of 15 LSTTL Loads
•
Wide Operating Voltage: V
CC
= 2 to 6 V
•
Low Input Current: 1
µA
max
•
Low Quiescent Supply Current: I
CC
(static) = 4
µA
max (Ta = 25°C)
•
Ordering Information
Part Name
HD74HC564P
HD74HC574P
HD74HC564FPEL
HD74HC574FPEL
HD74HC564RPEL
Package Type
DILP-20 pin
SOP-20 pin (JEITA)
SOP-20 pin (JEDEC)
Package Code
(Previous Code)
PRDP0020AC-B
(DP-20NEV)
PRSP0020DD-B
(FP-20DAV)
Package
Abbreviation
P
FP
—
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
Taping Abbreviation
(Quantity)
PRSP0020DC-A
RP
(FP-20DBV)
Note: Please consult the sales office for the above package availability.
Function Table
Output Control
L
L
L
H
Q
0
:
Q
0
:
L
X
Inputs
Clock
Outputs
Data
H
L
X
X
HD74HC564
L
H
Q
0
Z
HD74HC574
H
L
Q
0
Z
level of Q before the indicated Steady-sate input conditions were established.
complement of Q
0
or level of
Q
before the indicated Steady-state input Conditions were established.
Rev.2.00 Mar 30, 2006 page 1 of 9