HD74HC563, HD74HC573
Octal Transparent Latches (with 3-state outputs)
REJ03D0629-0200
(Previous ADE-205-509)
Rev.2.00
Mar 30, 2006
Description
When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D inputs and
the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be
retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control
input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of
the storage elements.
Features
•
High Speed Operation: t
pd
(Data to Q,
Q)
= 11 ns typ (C
L
= 50 pF)
•
High Output Current: Fanout of 15 LSTTL Loads
•
Wide Operating Voltage: V
CC
= 2 to 6 V
•
Low Input Current: 1
µA
max
•
Low Quiescent Supply Current: I
CC
(static) = 4
µA
max (Ta = 25°C)
•
Ordering Information
Part Name
HD74HC563P
HD74HC573P
HD74HC563FPEL
HD74HC573FPEL
HD74HC563RPEL
HD74HC573RPEL
HD74HC573TELL
Package Type
DILP-20 pin
SOP-20 pin (JEITA)
SOP-20 pin (JEDEC)
TSSOP-20 pin
Package Code
(Previous Code)
PRDP0020AC-B
(DP-20NEV)
PRSP0020DD-B
(FP-20DAV)
PRSP0020DC-A
(FP-20DBV)
PTSP0020JB-A
(TTP-20DAV)
Package
Abbreviation
P
FP
RP
T
—
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
ELL (2,000 pcs/reel)
Taping Abbreviation
(Quantity)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
Output Control
L
L
L
Q
0
:
Q
0
:
Latch Enable
H
H
L
Data
H
L
X
HD74HC563
L
H
Q
0
Outputs
HD74HC573
H
L
Q
0
Z
H
X
X
Z
level of Q before the indicated Steady-sate input conditions were established.
complement of Q
0
or level of
Q
before the indicated Steady-state input conditions were established.
Rev.2.00 Mar 30, 2006 page 1 of 10