HD74HC240
Octal Buffers/Line Drivers/Line Receivers
(with inverted 3-state outputs)
REJ03D0594–0200
(Previous ADE-205-471)
Rev.2.00
Jan 31, 2006
Description
The HD74HC240 is an inverting buffer and has two active low enables (1G and 2G). Each enable independently
controls 4 buffers. This device does not have schmitt trigger inputs.
Features
•
•
•
•
•
•
High Speed Operation: t
pd
= 10 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 15 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: I
CC
(static) = 4 µA max (Ta = 25°C)
Ordering Information
Part Name
HD74HC240P
HD74HC240FPEL
HD74HC240RPEL
Package Type
DILP-20 pin
SOP-20 pin (JEITA)
SOP-20 pin (JEDEC)
Package Code
(Previous Code)
PRDP0020AC-B
(DP-20NEV)
PRSP0020DD-B
(FP-20DAV)
Package
Abbreviation
P
FP
—
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
ELL (2,000 pcs/reel)
Taping Abbreviation
(Quantity)
PRSP0020DC-A
RP
(FP-20DBV)
PTSP0020JB-A
HD74HC240TELL
TSSOP-20 pin
T
(TTP-20DAV)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
G
H
L
L
H
L
X
Z
:
:
:
:
high level
low level
irrelevant
off (high-impedance) state of a 3-state output
A
X
H
L
Output
Y
Z
L
H
Rev.2.00 Jan 31, 2006 page 1 of 7