HD74HC165
V
CC
Clock Inhibit
(Clock)
(See notes 3)
50%
GND
t
rem
V
CC
Clock
(Clock Inhibit)
50%
50%
50%
GND
t
su
t
w
(clock)
V
CC
F, H
(See notes
1 and 2)
50%
50%
t
su
t
h
t
w
(load)
90%
Shift / Load
50%
10%
6ns
t
PHL
90%
Q
H
t
THL
t
PLH
90%
Q
H
50%
10%
t
TLH
t
THL
50%
10%
t
PLH
90%
50%
10%
t
TLH
t
PHL
90%
50%
10%
V
OL
50%
50%
50%
50%
t
PLH
t
PHL
t
PLH
t
PHL
V
OH
V
OL
90%
50%
10%
6ns
t
PHL
t
PLH
t
PHL
t
PLH
V
OH
50%
50%
50%
GND
t
h
50%
50%
GND
t
w
(load)
V
CC
Notes 1. The remaining six data inputs and the serial input are low.
2. Prior to test, high-level data is loaded into H input.
3. Disable while clock is high.
4. Input pulse : PRR
≤
1MHz, duty cycle 50%
Rev.3.00, Jan 31, 2006 page 6 of 7