HD74AC74
Dual D-Type Positive Edge-Triggered Flip-Flop
REJ03D0277–0200Z
(Previous ADE-205-361 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q,
Q)
outputs.
Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a
voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the
Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the Clock Pulse input.
Features
Asynchronous Inputs:
Low input to
S
D
(Set) sets Q to High level
Low input to
C
D
(Clear) sets Q to Low level
Clear and Set are independent of clock
Simultaneous Low on
C
D
and
S
D
makes both Q and
Q
High
•
Outputs Source/Sink 24 mA
•
Ordering Information
Part Name
HD74AC74P
HD74AC74FPEL
HD74AC74RPEL
HD74AC74TELL
Package Type
DIP-14 pin
SOP-14 pin (JEITA)
SOP-14 pin (JEDEC)
TSSOP-14 pin
Package Code Package Abbreviation Taping Abbreviation (Quantity)
DP-14, -14AV
FP-14DAV
FP-14DNV
TTP-14DV
P
FP
RP
T
—
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Pin Arrangement
C
D1
1
D
1
2
CP
1
3
S
D1
4
Q
1
5
Q
1
6
GND 7
D
2
C
D2
CP
2
S
D2
CP
1
D
1
S
D1
C
D1
14 V
CC
13
C
D2
12 D
2
11 CP
2
10
S
D2
9 Q
2
8
Q
2
Q
1
Q
1
Q
2
Q
2
(Top view)
Rev.2.00, Jul.16.2004, page 1 of 7
RENESAS [ RENESAS TECHNOLOGY CORP ]
