Pin No.
FP-80A, CP-84,
TFP-80C CG-84
Type
Symbol
I/O Name and Function
Bus control
WAIT
13
25
I
Wait: Requests the CPU to insert wait
states into the bus cycle when an
external address is accessed.
RD
WR
AS
17
16
15
29
28
27
O
O
O
Read: Goes low to indicate that the
CPU is reading an external address.
Write: Goes low to indicate that the
CPU is writing to an external address.
Address strobe: Goes low to indicate
that there is a valid address on the
address bus.
Interrupt signals NMI
6
17
I
Nonmaskable interrupt: Highest-
priority interrupt request. The NMIEG
bit in the system control register
(SYSCR) determines whether the
interrupt is recognized at the rising or
falling edge of the NMI input.
IRQ0 to
18 to 20, 30 to 32,
78 to 80, 9 to 11,
I
I
Interrupt request 0 to 7: Maskable
interrupt request pins.
IRQ7
27, 28
39, 40
Operating control MD1
MD0
4,
5
15,
16
Mode: Input pins for setting the MCU
mode operating mode according to the
table below.
MD1 MD0 Mode
Description
*
Mode 0 Illegal setting
0
0
0
1
Mode 1 Expanded mode
with on-chip ROM
disabled
1
1
0
1
Mode 2 Expanded mode
with on-chip ROM
enabled
Mode 3 Single-chip mode
Note: * In the H8/3337SF (S-mask model,
single-power-supply on-chip flash
memory version), the settings MD1
= MD0 = 0 are used when boot
mode is set. For details, see
section 21.3, On-Board
Programming Modes.
Do not change the mode pin settings while
the chip is operating.
20
RENESAS [ RENESAS TECHNOLOGY CORP ]
