13.3.4 Slave Transmit Operation..................................................................................... 300
13.3.5 Slave Receive Operation ...................................................................................... 302
13.3.6 IRIC Set Timing and SCL Control....................................................................... 303
13.3.7 Noise Canceler...................................................................................................... 304
13.3.8 Sample Flowcharts ............................................................................................... 305
13.4 Application Notes.............................................................................................................. 309
Section 14 Host Interface (H8/3337 Series Only)...................................................... 315
14.1 Overview............................................................................................................................ 315
14.1.1 Block Diagram...................................................................................................... 316
14.1.2 Input and Output Pins........................................................................................... 317
14.1.3 Register Configuration ......................................................................................... 318
14.2 Register Descriptions......................................................................................................... 319
14.2.1 System Control Register (SYSCR) ...................................................................... 319
14.2.2 Host Interface Control Register (HICR) .............................................................. 319
14.2.3 Input Data Register 1 (IDR1) ............................................................................... 320
14.2.4 Output Data Register 1 (ODR1)........................................................................... 321
14.2.5 Status Register 1 (STR1)...................................................................................... 321
14.2.6 Input Data Register 2 (IDR2) ............................................................................... 322
14.2.7 Output Data Register 2 (ODR2)........................................................................... 323
14.2.8 Status Register 2 (STR2)...................................................................................... 323
14.2.9 Serial/Timer Control Register (STCR) ................................................................ 325
14.3 Operation ........................................................................................................................... 326
14.3.1 Host Interface Operation ...................................................................................... 326
14.3.2 Control States ....................................................................................................... 326
14.3.3 A20 Gate................................................................................................................ 327
14.4 Interrupts............................................................................................................................ 330
14.4.1 IBF1, IBF2............................................................................................................ 330
14.4.2 HIRQ11, HIRQ1, and HIRQ12................................................................................ 330
14.5 Application Note................................................................................................................ 331
Section 15 A/D Converter ................................................................................................. 333
15.1 Overview............................................................................................................................ 333
15.1.1 Features ................................................................................................................ 333
15.1.2 Block Diagram...................................................................................................... 334
15.1.3 Input Pins.............................................................................................................. 335
15.1.4 Register Configuration ......................................................................................... 336
15.2 Register Descriptions......................................................................................................... 337
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 337
15.2.2 A/D Control/Status Register (ADCSR)................................................................ 338
15.2.3 A/D Control Register (ADCR)............................................................................. 340
15.3 CPU Interface .................................................................................................................... 340
15.4 Operation ........................................................................................................................... 342
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RENESAS [ RENESAS TECHNOLOGY CORP ]
