Port 9
Pin configuration in master mode,
or in slave mode when STAC bit is 0
P91/IRQ1/EIOW*2
P91 (input/output)/IRQ1 (input)
*2
P90/IRQ2/ADTRG/ECS2
P90 (input/output)/IRQ2 (input)/ADTRG (input)
Pin configuration in slave mode
when STAC bit is 1
IRQ1 (input)/EIOW*2 (input)
IRQ2 (input)/ECS2*2 (input)
Note: *2 The EIOW and ECS2 pin functions apply to the H8/3337 Series only. The H8/3397 Series
does not support a host interface, and therefore does not have these pin functions.
Figure 7.17 Port 9 Pin Configuration (cont)
7.10.2
Register Configuration and Descriptions
Table 7.18 summarizes the port 9 registers.
Table 7.18 Port 9 Registers
Name
Abbreviation
Read/Write Initial Value
Address
Port 9 data direction register
P9DDR
W
H'40 (modes 1 and 2) H'FFC0
H'00 (mode 3)
Port 9 data register
P9DR
R/W*1
Undetermined*2
H'FFC1
Notes: *1 Bit 6 is read-only.
*2 Bit 6 is undetermined. Other bits are initially 0.
152
RENESAS [ RENESAS TECHNOLOGY CORP ]
