Appendix
Instruction Branch
Stack
Byte Data
Word Data Internal
Fetch
I
Addr. Read Operation Access
Access
M
Operation
N
Instruction Mnemonic
J
K
L
SHLL
SHLL.B Rd
1
1
1
1
1
1
1
1
2
3
5
2
3
4
1
2
1
3
1
1
1
1
2
1
1
2
1
3
2
1
SHLL.W Rd
SHLL.L ERd
SHLR
SHLR.B Rd
SHLR.W Rd
SHLR.L ERd
SLEEP
STC
SLEEP
STC CCR, Rd
STC CCR, @ERd
STC CCR, @(d:16,ERd)
STC CCR, @(d:24,ERd)
STC CCR,@-ERd
STC CCR, @aa:16
STC CCR, @aa:24
SUB.B Rs, Rd
1
1
1
1
1
1
2
SUB
SUB.W #xx:16, Rd
SUB.W Rs, Rd
SUB.L #xx:32, ERd
SUB.L ERs, ERd
SUBS #1/2/4, ERd
SUBX #xx:8, Rd
SUBX. Rs, Rd
SUBS
SUBX
TRAPA
XOR
TRAPA #xx:2
1
2
4
XOR.B #xx:8, Rd
XOR.B Rs, Rd
XOR.W #xx:16, Rd
XOR.W Rs, Rd
XOR.L #xx:32, ERd
XOR.L ERs, ERd
XORC #xx:8, CCR
XORC
Notes: 1. n: Specified value in R4L and R4. The source and destination operands are accessed
n+1 times respectively.
2. Cannot be used in this LSI.
Rev. 3.00 Sep. 10, 2007 Page 487 of 528
REJ09B0216-0300
RENESAS [ RENESAS TECHNOLOGY CORP ]
