Appendix
Table A.3 Number of Cycles in Each Instruction
Access Location
On-Chip Peripheral Module
Execution Status
(Instruction Cycle)
On-Chip Memory
Instruction fetch
SI
2
—
Branch address read
Stack operation
SJ
SK
SL
SM
SN
Byte data access
Word data access
Internal operation
2 or 3*
2 or 3*
1
Note:
*
Depends on which on-chip peripheral module is accessed. See section 21.1, Register
Addresses (Address Order).
Rev. 3.00 Sep. 10, 2007 Page 478 of 528
REJ09B0216-0300