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HD6417709SF133B 参数 Datasheet PDF下载

HD6417709SF133B图片预览
型号: HD6417709SF133B
PDF下载: 下载PDF文件 查看货源
内容描述: 瑞萨32位RISC单片机超级RISC引擎族/ SH7700系列 [Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 807 页 / 4409 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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3.4  
MMU Functions  
3.4.1  
MMU Hardware Management  
There are two kinds of MMU hardware management as follows:  
1. The MMU decodes the virtual address accessed by a process and performs address translation  
by controlling the TLB in accordance with the MMUCR settings.  
2. In address translation, the MMU receives page management information from the TLB, and  
determines the MMU exception and whether the cache is to be accessed (using the C bit). For  
details of the determination method and the hardware processing, see section 3.5, MMU  
Exceptions.  
3.4.2  
MMU Software Management  
There are three kinds of MMU software management, as follows.  
1. MMU register setting. MMUCR setting, in particular, should be performed in areas P1 and P2  
for which address translation is not performed. Also, since SV and IX bit changes constitute  
address translation system changes, in this case, TLB flushing should be performed by  
simultaneously writing 1 to the TF bit also. Since MMU exceptions are not generated in the  
MMU disabled state with the AT bit cleared to 0, use in the disabled state must be avoided  
with software that does not use the MMU.  
2. TLB entry recording, deletion, and reading. TLB entry recording can be done in two ways by  
using the LDTLB instruction, or by writing directly to the memory-mapped TLB. For TLB  
entry deletion and reading, the memory allocation TLB can be accessed. See section 3.4.3,  
MMU Instruction (LDTLB), for details of the LDTLB instruction, and section 3.6,  
Configuration of Memory-Mapped TLB, for details of the memory-mapped TLB.  
3. MMU exception processing. When an MMU exception is generated, it is handled on the basis  
of information set from the hardware side. See section 3.5, MMU Exceptions, for details.  
When single virtual memory mode is used, it is possible to create a state in which physical  
memory access is enabled in the privileged mode only by clearing the share status bit (SH) to 0 to  
specify recording of all TLB entries. This strengthens inter-process memory protection, and  
enables special access levels to be created in the privileged mode only.  
Recording a 1-kbyte page TLB entry may result in a synonym problem. See section 3.4.4,  
Avoiding Synonym Problems.  
Rev. 5.00, 09/03, page 69 of 760  
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