TRr1
TRr2
TRr3
TRr4
TRr4w
TRr5
Trc
Trc
Trc
CKIO
tAD
A25–A0
tCSD
tRWD
RD/
tRASD
tRASD
tRASD
tCASD1
tCASD1
tCASD1
tWDD
D63–D0
(write)
tDACD
DACKn
(SA: IO ← memory)
tDACD
DACKn
(SA: IO → memory)
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.50 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh
(TRAS[2:0] = 001, TRC[2:0] = 001)
Rev. 6.0, 07/02, page 913 of 986