12.1.4 Register Configuration
Table 12.2 summarizes the TMU registers.
Table 12.2 TMU Registers
Initialization
Stand-
Manual by
Power-
On
Chan-
nel
Abbre-
Area 7
Access
Size
Name
viation R/W Reset Reset Mode Initial Value P4 Address Address
Com- Timer
mon output
control
TOCR R/W Ini-
Ini-
Held
H'00
H’FFD80000 H'1FD80000
8
tialized tialized
register
Timer
start
register
TSTR
R/W Ini-
Ini-
Ini-
H'00
H'00
H’FFD80004 H'1FD80004
H'FE100004 H'1E100004
8
8
1
*
tialized tialized tialized
TSTR2 3 R/W Ini-
tialized
Held
Held
Held
*
Timer
start
register 2
0
1
2
Timer
constant
register 0
TCOR0 R/W Ini-
Ini-
H'FFFFFFFF H’FFD80008 H'1FD80008 32
H'FFFFFFFF H’FFD8000C H'1FD8000C 32
tialized tialized
2
2
2
*
*
*
Timer
counter 0
TCNT0 R/W Ini-
Ini-
Held
tialized tialized
Timer
control
register 0
TCR0
R/W Ini-
Ini-
Held
H'0000
H’FFD80010 H'1FD80010 16
tialized tialized
Timer
constant
register 1
TCOR1 R/W Ini-
Ini-
Held
H'FFFFFFFF H’FFD80014 H'1FD80014 32
H'FFFFFFFF H’FFD80018 H'1FD80018 32
tialized tialized
Timer
counter 1
TCNT1 R/W Ini-
Ini-
Held
Held
tialized tialized
Timer
control
register 1
TCR1
R/W Ini-
Ini-
H'0000
H’FFD8001C H'1FD8001C 16
tialized tialized
Timer
constant
register 2
TCOR2 R/W Ini-
Ini-
Held
H'FFFFFFFF H’FFD80020 H'1FD80020 32
H'FFFFFFFF H’FFD80024 H'1FD80024 32
tialized tialized
Timer
counter 2
TCNT2 R/W Ini-
Ini-
Held
Held
tialized tialized
Timer
control
register 2
TCR2
R/W Ini-
Ini-
H'0000
H’FFD80028 H'1FD80028 16
H’FFD8002C H'1FD8002C 32
tialized tialized
Input
TCPR2
R
Held
Held
Held
Undefined
capture
register
Rev. 6.0, 07/02, page 293 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
