Effective address
31 25
13 12 1110
5 4
2
0
[11:5]
IIX
[12]
Entry
Longword (LW)
selection
selection
22
Address array
(way 0, way1)
8
Data array (way 0, way 1)
3
LRU
Tag address
V
LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
0
MMU
19
32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits
255
19 bits
1 bit
1 bit
Compare Compare
way 0 way 1
Read data
Hit signal
Figure 4.7 Configuration of Instruction Cache (SH7750R)
•
•
•
Tag
Stores the upper 19 bits of the 29-bit external address of the data line to be cached. The tag is
not initialized by a power-on or manual reset.
V bit (validity bit)
Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is
valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
Data array
The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized
by a power-on or manual reset.
Rev. 6.0, 07/02, page 110 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
