Section
Page
Item
Description
14.6 Configuration of the
DMAC (SH7750R)
574
Newly added
14.7 Register Descriptions
(SH7750R)
579
Newly added
14.8 Operation (SH7750R)
14.9 Usage Notes
586
591
592
609
Added
4.
Description amended
Newly added
9.
15.2.8 Serial Port Register
(SCSPTR1)
Bit 7
Description amended
16.1.2 Block Diagram
659
Figure 16.1 Block Diagram
of SCIF
Amended
16.1.3 Pin Configuration
660
667
Table 16.1 SCIF Pins
Bit 1
Note changed
16.2.6 Serial Control
Register (SCSCR2)
Description amended
16.2.7 Serial Status Register 669
(SCFSR2)
Bit 7—Receive Error (ER)
Note description
changed
672
672
Bit 3—Framing Error (FER)
Bit 2—Parity Error (PER)
Bits 10 to 8
Description changed
Description changed
SH7750R added
16.2.9 FIFO Control Register 676
(SCFCR2)
16.2.11 Serial Port Register
(SCSPTR2)
Figure 16.6 MRESET/SCK2 Deleted
Pin
16.3.2 Serial Operation
689
Figure 16.6 Sample SCIF
Initialization Flowchart
Amended
696
703
711
740
Serial Data Reception
Description added to 5.
Description amended
Description deleted
Amended
17.1 Overview
17.3.2 Pin Connections
18.1.3 Pin Configuration
Table 18.3 SCIF I/O Port
Pins
19.1.2 Block Diagram
752
Figure 19.1 Block Diagram
of INTC
Amended
19.1.4 Register Configuration 753
Table 19.2 INTC Registers
Description added to
table, Notes added and
amended
19.2.3 On-Chip Peripheral
Module Interrupts
757, 758
Description added and
amended
Rev. 6.0, 07/02, page xiv of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
