CD4066BMS
VC
tr = tf = 20ns
VOS 90%
20ns
1
0
10%
20ns
REP
RATE
VC = VDD
VDD
tr = tf = 20ns
VDD
VDD
ALL UNUSED TERMINALS
ARE CONNECTED TO VSS
VOS
50
pF
+10V
tr = tf = 20ns
VC
VDD = +10V
ALL UNUSED INPUTS
ARE CONNECTED TO VSS
CD4066BMS
1 OF 4 SWITCHES
VIS = +10V
CD4066BMS
1 OF 4 SWITCHES
VOS =
1
/
2
VOS
AT 1kHz
50
pF
1kΩ
VSS
1kΩ
VSS
FIGURE 8. PROPAGATION DELAY TPLH, TPHL CONTROL
SIGNAL OUTPUT. DELAY IS MEASURED AT VOS
LEVEL OF +10% FROM GROUND (TURN ON) OR
ON-STATE OUTPUT LEVEL (TURN OFF).
FIGURE 9. MAXIMUM ALLOWABLE CONTROL INPUT REPETI-
TION RATE
10
10
CLOCK
RESET
14
15
1
Q1 Q2
5
4
1
1
/
4
2
3
J2
7
J3
9
12
2
3
J2
7
J3
9
12
CLOCK
14
15
1
CD4066B
2
Q1 Q2
5
4
PE J1
J4 J5
EXT
RESET
PE J1
J4 J5
13
CD4018B
CD4018B
1
3
2
3
1
/
3
1
7
/
3
CD4049B
9
6
13
12
9
8
6
5
2
1
2
CD4049B
4
5
4
6
CD4001B
8
10
9
12
11
13
6
5
13
10
CD4001B
5
11
10
4
3
12
11
2
1
/ CD4049B
6
6
5
11
SIGNALS
OUTPUTS
LPF
CHANNEL 1
SIGNALS
INPUTS
12
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
1
4
8
11
CD4066B
12
2
10K
1
4
3
CD4066B
10K
3
9
4
10
10K
5
LPF
CHANNEL 2
1
/ CD4066B
4
3
8
11
PACKAGE COUNT
2 - CD4001B
1 - CD4049B
3 - CD4066BMS
2 - CD4018B
9
VDD
30% (VDD - VSS)
VSS
10K
LPF
CHANNEL 3
CLOCK
MAX. ALLOWABLE
SIGNAL LEVEL
CHAN. 1 CHAN. 2 CHAN. 3 CHAN. 4
10
10K
LPF
CHANNEL 4
FIGURE 10. 4 CHANNEL PAM MULTIPLEX SYSTEM DIAGRAM
7-972
RENESAS [ RENESAS TECHNOLOGY CORP ]
