CD4051BMS, CD4052BMS, CD4053BMS
Functional Diagrams
(Continued)
X CHANNELS IN/OUT
3
11
2
15
1
14
0
12
TG
16
VDD
TG
TG
COMMON X
OUT/IN
13
*
A
10
LOGIC
LEVEL
CONVERSION
BINARY
TO
1 OF 4
DECODER
WITH
INHIBIT
TG
TG
3
COMMON Y
OUT/IN
*
B
9
TG
*
INH
6
TG
TG
1
0
8
VSS
7
VEE
5
1
2
2
4
3
Y CHANNELS IN/OUT
CD4052BMS
VDD
* ALL INPUTS PROTECTED BY
STANDARD CMOS PROTECTION
NETWORK
VSS
BINARY TO 1 OF 2
DECODERS WITH
INHIBIT
16
VDD
IN/OUT
cy
3
cx
5
by
1
bx
2
ay
13
ax
12
OUT/IN
ax or ay
14
TG
OUT/IN
bx or by
15
TG
LOGIC
LEVEL
CONVERSION
TG
*
A
11
*
B
10
TG
*
C
9
TG
OUT/IN
cx or cy
4
*
INH
6
TG
8
VSS
7
VEE
CD4053BMS
7-939