APPENDIX
Appendix 6. Machine instructions
Symbol
IMP
Description
Implied addressing mode
Symbol
Description
E
Accumulator E
EH
EL
X
XH
XL
Y
YH
YL
S
REL
PC
PCH
PCL
PG
Accumulator E’s high-order 16 bits (Accumulator B)
Accumulator E’s low-order 16 bits (Accumulator A)
Index register X
Index register X’s high-order 8 bits
Index register X’s low-order 8 bits
Index register Y
Index register Y’s high-order 8 bits
Index register Y’s low-order 8 bits
Stack pointer
Relative address
Program counter
Program counter’s high-order 8 bits
Program counter’s low-order 8 bits
Program bank register
Immediate addressing mode
IMM
Accumulator addressing mode
Direct addressing mode
A
DIR
Direct indexed X addressing mode
Direct indexed Y addressing mode
Direct indirect addressing mode
Direct indexed X indirect addressing mode
Direct indirect indexed Y addressing mode
Direct indirect long addressing mode
Direct indirect long indexed Y addressing mode
Absolute addressing mode
DIR, X
DIR, Y
(DIR)
(DIR, X)
(DIR), Y
L(DIR)
L(DIR), Y
ABS
Absolute indexed X addressing mode
Absolute indexed Y addressing mode
Absolute long addressing mode
Absolute long indexed X addressing mode
Absolute indirect addressing mode
Absolute indirect long addressing mode
Absolute indexed X indirect addressing mode
Stack addressing mode
ABS, X
ABS, Y
ABL
DT
Data back register
Direct page register 0
DPR0
DPR0H
DPR0L
DPRn
DPRnH
DPRnL
PS
PSH
PSL
PSL(bit n)
M
ABL, X
(ABS)
L(ABS)
(ABS, X)
STK
Direct page register 0’s high-order 8 bits
Direct page register 0’s low-order 8 bits
Direct page register n
Direct page register n’s high-order 8 bits
Direct page register n’s low-order 8 bits
Processor status register
Processor status register’s high-order 8 bits
Processor status register’s low-order 8 bits
nth bit in processor status register
Contents of memory
Contents of memory at address indicated by stack
pointer
Relative addressing mode
REL
Direct bit relative addressing mode
Absolute bit relative addressing mode
Stack pointer relative addressing mode
Stack pointer relative indirect indexed Y addressing
mode
DIR, b, R
ABS, b, R
SR
(SR), Y
M(S)
Block transfer addressing mode
Multiplied accumulation addressing mode
BLK
M(bit n)
Mn
nth bit of memory
Multiplied
n-bit memory’s address or contents
Immediate value (8 bits or 16 bits)
n-bit immediate value
16-bit immediate value’s high-order 8 bits
16-bit immediate value’s low-order 8 bits
Value of 24-bit address’s high-order 8 bits (A23–A16)
Value of 24-bit address’s middle-order 8 bits (A15–A8)
Value of 24-bit address’s low-order 8 bits (A7–A0)
Effective address (16 bits)
accumulation
op
n
IMM
IMMn
IMMH
IMML
ADH
ADM
ADL
EAR
EARH
EARL
imm
immn
dd
Instruction code (Op code)
Number of cycles
Number of bytes
#
Carry flag
C
Z
Zero flag
Interrupt disable flag
Decimal operation mode flag
Index register length selection flag
Data length selection flag
Overflow flag
I
D
x
Effective address’s high-order 8 bits
Effective address’s low-order 8 bits
8-bit immediate value
m
V
N
IPL
+
Negative flag
n-bit immediate value
Processor interrupt priority level
Addition
Displacement for DPR (8 bits or 16 bits)
Number of transfer bytes, rotation or repeated operations
Number of registers pushed or pulled
Operand to specify transfer source
Operand to specify transfer destination
i
i1, i2
source
dest
Subtraction
Multiplication
–
✕
÷
Division
Logical AND
Logical OR
Logical exclusive OR
Absolute value
| |
Negation
Movement to the arrow direction
Movement to the arrow direction
Exchange
→
←
Accumulator
Acc
AccH
AccL
A
Accumulator’s high-order 8 bits
Accumulator’s low-order 8 bits
Accumulator A
Accumulator A’s high-order 8 bits
Accumulator A’s low-order 8 bits
Accumulator B
AH
AL
B
Accumulator B’s high-order 8 bits
Accumulator B’s low-order 8 bits
BH
BL
7906 Group User’s Manual Rev.2.0
20-55
RENESAS [ RENESAS TECHNOLOGY CORP ]
