APPENDIX
Appendix 2. Control registers
b7 b6 b5 b4 b3 b2 b1 b0
Port P2 pin function control register (Address AE16
)
0
Bit
0
Bit name
Function
At reset R/W Reference
6-18
8-6
0
RW
Pin TB0IN select bit
0 : Allocate pin TB0IN to P5
1 : Allocate pin TB0IN to P2
5
.
.
4
9-9
Pin TB1IN select bit
Pin TB2IN select bit
0 : Allocate pin TB1IN to P5
1 : Allocate pin TB1IN to P2
6
.
.
1
2
3
0
0
0
RW
RW
RW
5
0 : Allocate pin TB2IN to P5
1 : Allocate pin TB2IN to P2
7
6
.
.
Pin INT3/RTPTRG0 select bit
0: Allocate pin INT
1: Allocate pin INT
3
/RTPTRG0 to P7
4
.
.
(Note)
3/RTPTRG0 to P2
7
6 to 4
7
Nothing is assigned.
Fix this bit to “0.”
Undefined
—
0
RW
Note: When allocating pin INT
3
/RTPTRG0 to P7
4
, be sure the D-A output enable bit (bit 1 at address 9616) = “0” (output disabled).
1
b7 b6 b5 b4 b3 b2 b1 b0
Clock control register 0 (Address BC16)
1
1
Function
Bit
Bit name
Fix this bit to “1.”
At reset
R/W
Reference
4-6
4-7
1
1
0
1
RW
RW
PLL circuit operation enable bit
0 : PLL frequency multiplier is inactive, and pin VCONT
is invalid. (Floating)
1 : PLL frequency multiplier is active, and pin VCONT is valid.
(Note 1)
b3 b2
RW
RW
1
0
2
3
PLL multiplication ratio select bits
0 0 : Do not select.
0 1 : ꢀ 2
1 0 : ꢀ 3
1 1 : ꢀ 4
(Note 2)
RW
RW
1
0
4
5
Fix this bit to “1.”
0 : fXIN
1 : fPLL
System clock select bit
(Note 3)
See Table 4.2.2.
RW
RW
0
0
6
7
Peripheral device’s clock select bit 0
Peripheral device’s clock select bit 1
Notes 1: Clear this bit to “0” if the PLL frequency multiplier needs not to be active.
In the stop and flash memory parallel I/O modes, the PLL frequency multiplier is inactive and pin VCONT is invalid regard-
less of the contents of this bit.
2: Rewriting of these bits must be performed simultaneously with clearance of the system clock select bit (bit 5) to “0.”
Then, set bit 5 to “1” 2 ms after the rewriting of these bits. (After reset, these bits are allowed to be changed only once.)
3: Clearance of the PLL circuit operation enable bit (bit 1) to “0” clears the system clock select bit to “0.” Also, while the PLL
circuit operation enable bit = “0,” nothing can be written to the system clock select bit. (Fixed to be “0.”)
Before setting of the system clock select bit to “1” after reset, it is necessary to insert an interval of 2 ms after the
stabilization of f(XIN).
7906 Group User’s Manual Rev.2.0
20-42
RENESAS [ RENESAS TECHNOLOGY CORP ]
