APPENDIX
Appendix 2. Control registers
b7 b6 b5 b4 b3 b2 b1 b0
Particular function select register 0 (Address 6216)
0 0 0 0 0 0
Bit
0
Bit name
Function
0 : STP instruction is valid.
At reset R/W
Reference
15-4
0
RW
STP instruction invalidity select bit
1 : STP instruction is invalid.
(Note)
4-10
15-5
16-4
0
RW
(Note)
0 : Oscillation circuit is active. (Oscillator is connected.)
Watchdog timer is used at stop mode termination.
1 : Oscillation circuit is inactive. (External clock is
input.)
1
External clcok input select bit
When the system clock select bit (bit 5 at address BC16) = “0,”
watchdog timer is not used at stop mode termination.
When the system clock select bit = “1,”
watchdog timer is used at stop mode termination.
Fix these bits to “000000.”
7 to 2
RW
0
Note: Writing to these bits requires the following procedure:
• Write “5516” to this register. (The bit status does not change only by this writing.)
• Succeedingly, write “0” or “1” to each bit.
Also, use the MOVMB (MOVM when m = 1) instruction or STAB (STA when m = 1) instruction.
If an interrupt occurs between writing of “5516” and next writing of “0” or “1,” latter writing may be ignored. When there is a
possibility that an interrupt occurs at the above timing, be sure to read this bit’s contents after writing of “0” or “1,” and verify
whether “0” or “1” has correctly been written or not.
b7 b6 b5 b4 b3 b2 b1 b0
Particular function select register 1 (Address 6316
)
0
0
Function
Bit
0
Bit name
At reset R/W
Reference
15-6
0 : Normal operation.
1 : During execution of STP instruction
STP-instruction-execution
status bit
(Note 1) RW
(Note 2)
0 : Normal operation.
1 : During execution of WIT instruction
WIT-instruction-execution
status bit
1
(Note 1) RW
(Note 2)
0
Fix this bit to “0.”
2
3
RW
System clock stop select bit
at WIT
0 : In the wait mode, system clock fsys is active.
1 : In the wait mode, system clock fsys is inactive.
16-5
8-15
0
RW
(Note 3)
0
0
0
RW
—
Fix this bit to “0.”
4
5
6
The value is “0” at reading.
Timer B2 clock source select bit 0 : External signal input to the TB2IN pin is counted.
(Valid in event counter mode.)
The value is “0” at reading.
RW
1 : fX32 is counted.
—
7
0
Notes 1: At power-on reset, this bit becomes “0.” At hardware reset or software reset, this bit retains the value just before reset.
2: Even when “1” is written, the bit status will not change.
3: Setting this bit to “1” must be performed just before execution of the WIT instruction. Also, after the wait state is termi-
nated, this bit must be cleared to “0” immediately.
7906 Group User’s Manual Rev.2.0
20-31
RENESAS [ RENESAS TECHNOLOGY CORP ]
