POWER SAVING FUNCTIONS
16.2 Inactivity of system clock in wait mode
16.2 Inactivity of system clock in wait mode
In the wait mode, if there is not need to operate the internal peripheral devices, setting the system clock
stop select bit at WIT (See Figure 16.1.3.) to “1” makes the following clocks inactive: the operating clocks
for the internal peripheral devices and fsys. This saves the power consumption of the microcomputer.
Table 16.2.1 lists the states and operations in the wait mode and after this mode is terminated.
Table 16.2.1 States and operations in wait mode and after this mode is terminated
Item
System clock is active. (bit 3 at address 6316 = 0) System clock is inactive. (bit 3 at address 6316 = 1)
Oscillation
Active.
PLL frequency multiplier
φCPU, φBIU
Operates (Note).
Inactive.
Inactive.
Active.
fsys, Clock φ1,
f1 to f4096
Inactive.
Wf32, Wf512
Timers A, B
Can operate only in the event counter mode.
Operates.
Operates.
Operates.
Operates.
Stopped.
Serial I/O
Can operate only when an external clock is selected.
A-D converter
D-A converter
Watchdog timer
Pins
Stopped.
Stopped.
Retains the state at the WIT instruction execution.
Termination due to Supply of φCPU, φBIU starts immediately just after termination.
interrupt request
occurrence
Termination due to Operation after hardware reset
hardware reset
Note: This applies when the PLL circuit operation enable bit (bit 1 at address BC16) = “1.”
7906 Group User’s Manual Rev.2.0
16-6
RENESAS [ RENESAS TECHNOLOGY CORP ]
