A-D CONVERTER
12.3 A-D conversion method
Table 12.3.2 Change of successive approximation register and Vref during A-D conversion (8-bit resolution)
Successive approximation register
Change of Vref
b9
1 0 0 0 0 0 0
b0
V
V
V
V
REF
[V]
0
0 0
A-D converter halt
1st comparison
2nd comparison
3rd comparison
2
REF
V
REF
1
0 0 0 0 0 0 0 0
0
[V]
–
±
±
2
2048
V
REF
+
•n
•n
9
9
= 1
= 0
4
REF
V
REF
V
REF
n9
1 0
0
0 0 0
0
0 0
[V]
–
V
REF
–
2
4
2048
4
1st comparison result
0 0 0 0 0 0 0
V
V
REF
+
•n
8
= 1
V
4
REF
V
REF
V
REF
REF
8
REF
n9
n8
1
–
[V]
±
8
2048
2
–
•n
8
= 0
8
2nd comparison result
:
:
:
:
:
:
V
REF
V
REF
V
REF
V
REF
V
REF
n
9
9
n
8
8
n
7
n
6
6
n
5
n
4
4
n
3
1
0 0
0 0
±
±
± ...... ±
–
[V]
8th comparison
2
4
8
256
2048
Conversion completed
n
n
n7
n
n5
n
n
3
n2
Table 12.3.3 Change of successive approximation register and Vref during A-D conversion (10-bit resolution)
Successive approximation register
Change of Vref
b9
b0
V
V
V
V
REF
[V]
A-D converter halt
1st comparison
1 0 0 0 0 0 0 0 0 0
2
REF
V
REF
1
0
0 0 0 0 0 0 0 0
–
[V]
2
2048
V
REF
+
•n
•n
9
9
= 1
= 0
4
REF
REF
V
REF
V
REF
n9
±
2nd comparison
3rd comparison
[V]
1 0 0 0 0 0 0 0 0
1st comparison result
–
V
2
4
2048
–
4
V
8
REF
•n
•n
8
8
= 1
= 0
+
REF
V
REF
V
REF
V
REF
±
±
±
[V]
n9
n8
1 0 0 0 0 0 0
2nd comparison result
0
–
8
2
4
2048
V
REF
–
8
:
:
:
:
:
:
V
REF
V
REF
V
REF
V
REF
V
REF
n
9
9
n
8
n
7
7
n
6
6
n
5
5
n
4
4
n
3
3
n
2
2
n
1
1
10th comparison
±
± ...... ±
[V]
–
8
2
4
1024
2048
Conversion completed
n
n8
n
n
n
n
n
n
n
1
n0
7906 Group User’s Manual Rev.2.0
12-13
RENESAS [ RENESAS TECHNOLOGY CORP ]
