THREE-PHASE WAVEFORM MODE
10.2 Block description
(1) W-phase fixed output’s polarity set bit (bit 0)
Clearance of this bit to “0” fixes the output level at the W-phase waveform output pin to “H”; vice
versa, setting of this bit to “1” fixes the output level at the W-phase waveform output pin to “L.”
The output level at the W-phase waveform output pin is reversed.
Note that this bit is valid only when the W-phase output fix bit (bit 0 at address A816) = “1.”
(2) V-phase fixed output’s polarity set bit (bit 1)
Clearance of this bit to “0” fixes the output level at the V-phase waveform output pin to “H”; vice versa,
setting of this bit to “1” fixes the output level at the V-phase waveform output pin to “L.”
The output level at the V-phase waveform output pin is reversed.
Note that this bit is valid only when the V-phase output fix bit (bit 1 at address A816) = “1.”
(3) U-phase fixed output’s polarity set bit (bit 2)
Clearance of this bit to “0” fixes the output level at the U-phase waveform output pin to “H”; vice versa,
setting of this bit to “1” fixes the output level at the U-phase waveform output pin to “L.”
The output level at the U-phase waveform output pin is reversed.
Note that this bit is valid only when the U-phase output fix bit (bit 2 at address A816) = “1.”
(4) V-phase output polarity set buffer (bit 4) (in three-phase mode 0)
This bit serves as the buffer to set the V-phase output polarity. (Refer to section “10.2.9 Output
polarity set toggle flip-flop.”)
Interrupt request interval set bit (bit 4) (in three-phase mode 1)
Clearance of this bit to “0” generates a timer A3 interrupt request at every second time; vice versa,
setting of this bit to “1” generates a timer A3 interrupt request at every forth time.
(Refer to section “10.4 Three-phase mode 1.”)
(5) U-phase output polarity set buffer (bit 5) (in three-phase mode 0)
This bit serves as the buffer to set the U-phase output polarity. (Refer to section “10.2.9 Output
polarity set toggle flip-flop.”)
Interrupt validity output select bit (bit 5) (in three-phase mode 1)
Clearance of this bit to “0” generates a timer A3 interrupt request at every even-numbered underflow
of timer A3; vice versa, setting of this bit to “1” generates a timer A3 interrupt request at every odd-
numbered underflow of timer A3.
(Refer to section “10.4 Three-phase mode 1.”)
7906 Group User’s Manual Rev.2.0
10-11
RENESAS [ RENESAS TECHNOLOGY CORP ]
