DEBUG FUNCTION
17.3 Address matching detection mode
17.3.2 Operations in address matching detection mode
ꢀ Setting the detect enable bit to “1” initiate to compare the contents of PG and PC with one of the con-
tents of the following registers. This comparison is performed at each op-code fetch:
• When the address matching detection 0 is selected, the contents of the address compare register 0
are used for the above comparison.
• When the address matching detection 1 is selected, the contents of the address compare register 1
are used for the above comparison.
• When the address matching detection 2 is selected, the contents of the address compare register 0
or 1 are used for the above comparison.
ꢀ When the address which matches with the above register’s contents is detected, an address matching
detection interrupt request occurs, and then, this request will be accepted.
ꢀ Perform the necessary processing with an address matching detection interrupt routine.
ꢀ The contents of PG, PC, and PS at acceptance of the address matching detection interrupt request are
saved onto the stack area. Therefore, be sure to rewrite the above contents of PG and PC to a certain
return address, and return to the address by using the RTI instruction.
When an address matching detection interrupt request has been accepted, the interrupt disable flag (I) is
set to “1”; the processor interrupt priority level (IPL) does not change.
Figures 17.3.2 and 17.3.3 show the examples of the ROM correct processing using the address matching
detection mode.
7905 Group User’s Manual Rev.1.0
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RENESAS [ RENESAS TECHNOLOGY CORP ]
