WATCHDOG TIMER
14.2 Operation description
14.2 Operation description
The operations of the watchdog timer are described below.
14.2.1 Basic operation
ꢀ Watchdog timer starts counting down from “FFF16.”
ꢀ When the watchdog timer’s most significant bit becomes “0” (counted 2048 times), a watchdog timer
interrupt request occurs. (See Table 14.2.1.)
ꢀ When the interrupt request occurs in above ꢀ, a value of “FFF16” is set to the watchdog timer.
A watchdog timer interrupt is a non-maskable interrupt. When a watchdog timer interrupt request is accepted,
the processor interrupt priority level (IPL) is set to “111 .”
2
Table 14.2.1 Occurrence interval of watchdog timer
interrupt request
Watchdog timer
f(fsys) = 20 MHz
frequency select bit
Count source Occurrence interval (Note)
0
1
Wf512
Wf32
52.43 ms
3.28 ms
Note: This applies when the peripheral device’s clock
select bits 1, 0 (bits 7, 6 at address BC16) = “002.”
7905 Group User’s Manual Rev.1.0
14-5
RENESAS [ RENESAS TECHNOLOGY CORP ]
