PULSE OUTPUT PORT MODE
9.2 Block description of pulse output port 0
9.2.1 Waveform output mode register
Figure 9.2.2 shows the structure of the waveform output mode register (pulse output port 0).
b7 b6 b5 b4 b3 b2 b1 b0
Waveform output mode register (Address A616
)
Bit
0
Bit name
Function
At reset R/W
Waveform output select bits
See Table 9.2.1.
0
0
0
RW
RW
RW
(Note)
1
2
0 : Pulse mode 0
1 : Pulse mode 1
0
RW
Pulse output mode select bit
3
Pulse width modulation timer
select bits
0
0
0
RW
RW
RW
4
5
6
See Table 9.2.2.
When pulse mode 0 is selected,
Waveform output control bit 0
Waveform output control bit 1
0: RTP1
1: RTP1
0
to RTP1
to RTP1
3
: pulse outputs are disabled.
: pulse outputs are enabled.
0
3
When pulse mode 1 is selected,
0: RTP1
1: RTP1
2
, RTP1
, RTP1
3
: pulse outputs are disabled.
: pulse outputs are enabled.
2
3
When pulse mode 0 is selected,
7
0
RW
0 : RTP0
0
to RTP0
to RTP0
3
: pulse outputs are disabled.
: pulse outputs are enabled.
1 : RTP0
0
3
When pulse mode 1 is selected,
0 : RTP0
0
to RTP0
3
, RTP1
0, RTP11: pulse outputs
are disabled.
1 : RTP0
0
to RTP0
3
RTP10, RTP1
1: pulse outputs
are enabled.
Note: When not using pulse output port 0 and three-phase waveform mode, be sure to fix these bits to “000 .”
2
Fig. 9.2.2 Structure of waveform output mode register (pulse output port 0)
7905 Group User’s Manual Rev.1.0
9-5
RENESAS [ RENESAS TECHNOLOGY CORP ]
