M16C/6KA Group
Memory
Operation of Functional Blocks
The M16C/6KA (144-pin version) group accommodates certain units in a single chip. These units include
ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/
logic operations. Also peripheral units such as timers, serial I/O, A-D converter, host bus interface, PWM
2
output, I C BUS interface, PS2 interface and I/O ports are included.
The following explains each unit.
Memory
Fig.CA-1 is the memory map. The address space extends up to 1M bytes from address 0000016 to FFFFF16.
There is 128K bytes of internal ROM from E000016 to FFFFF16. The vector table for fixed interrupts such as
_______
the reset and NMI are mapped from FFFDC16 to FFFFF16. The starting address of the interrupt routine is
stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal
register (INTB). See the section on interrupts for details.
From 0040016 to the address increasing direction RAM is allocated. For example, in the M306KAFCLRP, 5K
bytes of internal RAM is mapped to the space from 0040016 to 017FF16. In addition to storing data, the RAM
also stores the stack used when calling subroutines and when interrupts are generated.
The SFR area is mapped from 0000016 to 003FF16. This area accommodates the control registers for pe-
ripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Fig.CA-2 to CA-5 are location of
peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be
used for other purposes.
The special page vector table is mapped from FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can
be used as 2-byte instructions, reducing the number of program steps.
0000016
SFR area
For details, see
Fig.CA-2 to Fig.CA-4
0040016
Internal RAM area
FFE0016
017FF16
Special page
vector table
FFFDC16
Undefined instruction
Overflow
Inhibited
BRK instruction
Address match
Single step
Watchdog timer
DBC
E000016
FFFFF16
Internal ROM area
NMI
Reset
FFFFF16
Fig.CA-1 Memory map
Rev.1.00 Jul 16, 2004 page 12 of 266
REJ03B0100-0100Z
RENESAS [ RENESAS TECHNOLOGY CORP ]
