R32C/118 Group
1. Overview
1.4
Pin Assignments
Figure 1.3 and Figure 1.4 show the pin assignments (top view) and Table 1.7 to Table 1.13 show the pin
characteristics.
(Note 1)
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
IIO0_0 / IIO1_0 / D8 / P1_0
AN0_7 / D7 / P0_7
P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6
P4_5 / CS2 / A21 / CLK6
P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6
P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6
P12_5 / D21
AN0_6 / D6 / P0_6
AN0_5 / D5 / P0_5
AN0_4 / D4 / P0_4
WR3 / BC3 / P11_4
P12_6 / D22
IIO1_3 / RTS8 / CTS8 / WR2 / CS3 / P11_3
IIO1_2 / RXD8 / CS2 / P11_2
IIO1_1 / CLK8 / CS1 / P11_1
IIO1_0 / TXD8 / CS0 / P11_0
AN0_3 / D3 / P0_3
P12_7 / D23
P5_0 / WR0 / WR
P5_1 / WR1 / BC1
P5_2 / RD
P5_3 / CLKOUT / BCLK
P13_0 / D24 / OUTC2_4
P13_1 / D25 / OUTC2_5
VCC
AN0_2 / D2 / P0_2
AN0_1 / D1 / P0_1
AN0_0 / D0 / P0_0
IIO0_7 / RTS6 / CTS6 / SS6 / AN15_7 / P15_7
IIO0_6 / CLK6 / AN15_6 / P15_6
IIO0_5 / RXD6 / SCL6 / STXD6 / AN15_5 / P15_5
IIO0_4 / TXD6 / SDA6 / SRXD6 / AN15_4 / P15_4
IIO0_3 / RTS7 / CTS7 / AN15_3 / P15_3
IIO0_2 / RXD7 / AN15_2 / P15_2
IIO0_1 / CLK7 / AN15_1 / P15_1
VSS
P13_2 / D26 / OUTC2_6
VSS
R32C/118 GROUP
(Note 2)
P13_3 / D27 / OUTC2_3
P5_4 / HLDA / CS1 / TXD7
P5_5 / HOLD / CLK7
PLQP0144KA-A
(144P6Q-A)
(Top view)
P5_6 / ALE / CS2 / RXD7
P5_7 / RDY / CS3 / CTS7 / RTS7
P13_4 / D28 / OUTC2_0 / ISTXD2 / IEOUT
P13_5 / D29 / OUTC2_2 / ISRXD2 / IEIN
P13_6 / D30 / OUTC2_1 / ISCLK2
P13_7 / D31 / OUTC2_7
P6_0 / TB0IN / CTS0 / RTS0 / SS0
P6_1 / TB1IN / CLK0
IIO0_0 / TXD7 / AN15_0 / P15_0
VCC
KI3 / AN_7 / P10_7
KI2 / AN_6 / P10_6
KI1 / AN_5 / P10_5
KI0 / AN_4 / P10_4
P6_2 / TB2IN / RXD0 / SCL0 / STXD0
P6_3 / TXD0 / SDA0 / SRXD0
P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2
P6_5 / CLK1
AN_3 / P10_3
AN_2 / P10_2
AN_1 / P10_1
AVSS
VSS
AN_0 / P10_0
P6_6 / RXD1 / SCL1 / STXD1
VCC
VREF
AVCC
P6_7 / TXD1 / SDA1 / SRXD1
STXD4 / SCL4 / RXD4 / ADTRG / P9_7
P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT / MSDA
(Note 3)
Notes:
1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins.
2. The following pins are 5 V tolerant inputs: P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7, P7_0 to P7_7, and P8_0 to P8_3.
3. The position of pin number 1 varies by product. Refer to the index mark in attached “Package Dimensions”.
Figure 1.3
Pin Assignment for the 144-pin Package (top view)
REJ03B0255-0110 Rev.1.10
Jun 23, 2010
Page 10 of 123
RENESAS [ RENESAS TECHNOLOGY CORP ]
