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RTL8306SD-VC-GR 参数 Datasheet PDF下载

RTL8306SD-VC-GR图片预览
型号: RTL8306SD-VC-GR
PDF下载: 下载PDF文件 查看货源
内容描述: [Micro Peripheral IC]
分类和应用:
文件页数/大小: 132 页 / 1325 K
品牌: REALTEK [ Realtek Semiconductor Corp. ]
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RTL8306SD/RTL8306SDM  
Datasheet  
Pin Name  
Pin  
No.  
Type  
Drive Description  
(MA)  
Default  
Value  
P4LNKSTA#  
49  
I (IPU)  
-
Port4 Link Status for MAC:  
This pin determines the link status of Port4 MAC in  
1
real-time when Port4 MAC works in MAC mode MII /  
PHY mode MII/RMII regardless of Port4 PHY circuit  
interface is disabled or worked in PHY mode MII/RMII.  
This pin is low active. Pulling this pin down sets the  
link status of PHY 5 MII register 1.2.  
1: No Link.  
0: Link  
Regardless of whether DISDUALMII=1 or =0, this pin  
provides real-time link status to Port4 MAC part in  
PHY 5 MII register 1.2 when Port4 MAC part is  
configured in MAC mode MII / PHY mode MII/RMII  
Mode  
When Port4 operates in UTP mode only, the MII/RMII  
1 interface is disabled and this pin has no function. It  
should be left floating.  
P4DUPSTA/HO  
ME_CRS  
48  
I (IPU)  
-
When HOMEPNA or HOMEPLUG mode is disabled  
(see Table 9, page 27, pin 92), this is a strapping pin.  
Upon reset  
1
Port4 Duplex Status:  
Port4 initial configuration pin for duplex upon reset for  
PHY in UTP mode, and strap duplex status for MAC of  
other modes upon reset.  
1: Full duplex  
0: Half duplex  
When enabling HOMEPNA or HOMEPLUG mode, this  
pin is the CRS signal pin of MII.  
P4SPDSTA  
47  
46  
I (IPU)  
-
-
Input upon reset  
Port4 Speed Status:  
Port4 initial configuration pin for speed status upon  
reset for PHY of UTP mode only, and strap speed status  
for MAC of other modes upon reset.  
1: 100Mbps  
1
1
0: 10Mbps  
P4FLCTRL/CPU  
I/O (IPU)  
Input upon reset  
_
Port4 Flow Control:  
interrupt#  
Port4 initial configuration pin for flow control upon  
reset for PHY of UTP mode, and strap flow control  
status for MAC of other modes upon reset.  
1: Enable Flow Control ability  
0: Disable Flow Control ability  
Output after reset:  
Provide interrupt signal to CPU when interrupt events  
occur.  
6-Port 10/100Mbps Single-Chip Dual MII/RMII Switch Controller  
12  
Track ID: JATR-1076-21 Rev. 1.1  
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