RTL8169S-32/RTL8169S-64
Datasheet
Symbol
Type
Pin No.
(233BGA)
Description
Pin No.
(128QFP)
28
PCICLK
I
M1
PCI Clock. This clock input provides timing for all PCI
transactions and is input for the PCI device. Supports up to a
66MHz PCI clock.
DEVSELB
FRAMEB
S/T/S
S/T/S
68
61
T16
Device Select. As a bus master, the RTL8169S samples this
signal to insure that a PCI target recognizes the destination
address for the data transfer. As a target, the RTL8169S
asserts this signal low when it recognizes its target address
after FRAMEB is asserted.
Cycle Frame. As a bus master, this pin indicates the
beginning and duration of an access. FRAMEB is asserted
low to indicate the start of a bus transaction. While
FRAMEB is asserted, data transfer continues. When
FRAMEB is de-asserted, the transaction is in the final data
phase.
R13
As a target, the device monitors this signal before decoding
the address to check if the current transaction is addressed to
it.
GNTB
I
29
N2
Grant. This signal is asserted low to indicate to the
RTL8169S that the central arbiter has granted the ownership
of the bus to the RTL8169S. This input is used when the
device is acting as a bus master.
REQB
IDSEL
T/S
I
30
46
P2
Request. The RTL8169S will assert this signal low to
request the ownership of the bus from the central arbiter.
Initialization Device Select. This pin allows the device to
identify when configuration read/write transactions are
intended for it.
U6
INTAB
IRDYB
O/D
25
63
K3
Interrupt A. Used to request an interrupt. It is asserted low
when an interrupt condition occurs, as defined by the
Interrupt Status, Interrupt Mask.
S/T/S
R14
Initiator Ready. This indicates the initiating agent’s ability
to complete the current data phase of the transaction.
As a bus master, this signal will be asserted low when the
device is ready to complete the current data phase
transaction. This signal is used in conjunction with the
TRDYB signal. Data transaction takes place at the rising
edge of CLK when both IRDYB and TRDYB are asserted
low. As a target, this signal indicates that the master has put
data on the bus.
TRDYB
S/T/S
67
R16
Target Ready. This indicates the target agent’s ability to
complete the current phase of the transaction.
As a bus master, this signal indicates that the target is ready
for the data during write operations, or is ready to provide
the data during read operations. As a target, this signal will
be asserted low when the (slave) device is ready to complete
the current data phase transaction. This signal is used in
conjunction with the IRDYB signal. Data transaction takes
place at the rising edge of CLK when both IRDYB and
TRDYB are asserted low.
Integrated Gigabit Ethernet Controller (NIC)
7
Track ID: JATR-1076-21 Rev. 1.7
REALTEK [ Realtek Semiconductor Corp. ]
