RTL8110SC(L)
Datasheet
V_ih
V_test
CLK (@ Device #1)
CLK (@ Device #2)
T_skew
V_il
T_skew
V_ih
T_skew
V_test
V_il
Figure 16. Clock Skew Diagram
Table 19. Clock and Reset Specifications
66MHz
33MHz
Symbol
Symbol
Tcyc
Thigh
Tlow
--
Parameter
CLK Cycle Time
CLK High Time
CLK Low Time
CLK Slew Rate
RST# Slew Rate
CLK Skew
Min
15
6
6
1.5
50
Max
30
Min
30
11
11
1
Parameter
∞
ns
ns
ns
V/ns
mV/ns
ns
4
-
4
-
--
Tskew
50
1
2
7.7.3. PCI Transactions
CLK
1
2
3
4
5
6
7
8
9
10
FRAMEB
AD31-0
ADDRESS
BUS CMD
DATA
BE3-0B
C/BE3-0B
IRDYB
TRDYB
DEVSELB
Figure 17. I/O Read
Integrated Gigabit Ethernet Controller (LOM) (MiniPCI) 27
Track ID: JATR-1076-21 Rev. 1.2