RTL8101L
Datasheet
2. Features
2.1. Ethernet Controller Features
100 pin LQFP
Supports auxiliary power-on internal
Integrated Fast Ethernet MAC, Physical
chip, and transceiver in one chip
10Mbps and 100Mbps operation
Supports 10Mbps and 100Mbps N-way
Auto-negotiation
reset, for remote wake-up when main
power remains off
Supports auxiliary power auto-detect, and
sets the related capability of power
management registers in PCI
configuration space
PCI local bus single-chip Fast Ethernet
controller
Includes a programmable PCI burst size
and early Tx/Rx threshold
Complies with PCI Revision 2.2
Supports PCI clock 16.75MHz-40MHz
Supports PCI target fast back-to-back
transaction
Supports a 32-bit general-purpose timer
with the external PCI clock as clock
source to generate a timer-interrupt
Contains two large (2Kbyte) independent
receive and transmit FIFOs
Provides PCI bus master data transfers
and PCI memory space or I/O space
mapped data transfers of RTL8101L's
operational registers
Advanced power saving mode when
LAN function or wakeup function is not
used
Supports PCI VPD (Vital Product Data)
Supports ACPI, PCI power management
Supports 25MHz crystal or 25MHz OSC
as the internal clock source. The
frequency deviation of either crystal or
OSC must be within 50 PPM.
Uses 93C46 (64*16-bit EEPROM) to
store resource configuration, ID
parameter, and VPD data
Supports LED pins for various network
activity indications
Complies with to PC99/PC2001 standard
Supports Wake-On-LAN function and
remote wake-up (Magic Packet, LinkChg
and Microsoft® wake-up frame)
Supports 4 Wake-On-LAN (WOL)
signals (active high, active low, positive
pulse, and negative pulse)
Supports loopback capability
Half/Full duplex capability
Supports Full Duplex Flow Control
(IEEE 802.3x)
3.3V power supply, 3.3V and 5V I/O
tolerance
Interface for 128K byte (max) Boot ROM
for both EEPROM and Flash Memory
Single-Chip Fast Ethernet Controller and MC’97
Controller w/Power Management
2
Track ID: JATR-1076-21 Rev. 1.5
REALTEK [ Realtek Semiconductor Corp. ]
