ALC5642-VF
Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM .......................................................................................................................................................4
FIGURE 2. AUDIO MIXER PATH ...................................................................................................................................................5
FIGURE 3. DIGITAL MIXER PATH ................................................................................................................................................6
FIGURE 4. PIN ASSIGNMENTS ......................................................................................................................................................7
FIGURE 5. POWER ON/OFF SEQUENCE ......................................................................................................................................14
FIGURE 6. AUDIO CLOCK TREE .................................................................................................................................................16
FIGURE 7. SYSTEM CONNECTION FOR ASRC FUNCTION...........................................................................................................20
FIGURE 8. PCM MONO DATA MODE A FORMAT (BCLK POLARITY=0)..............................................................................22
FIGURE 9. PCM MONO DATA MODE A FORMAT (BCLK POLARITY=1)..............................................................................22
FIGURE 10. PCM MONO DATA MODE B FORMAT (BCLK POLARITY=0) ............................................................................23
FIGURE 11. PCM STEREO DATA MODE A FORMAT (BCLK POLARITY=0)............................................................................23
FIGURE 12. PCM STEREO DATA MODE B FORMAT (BCLK POLARITY=0)..............................................................................23
FIGURE 13. I2S DATA FORMAT (BCLK POLARITY=0).............................................................................................................24
FIGURE 14. LEFT-JUSTIFIED DATA FORMAT (BCLK POLARITY=0) ........................................................................................24
FIGURE 15. 4-CHANNEL RECORDING PATH ................................................................................................................................25
FIGURE 16. 4-CHANNEL PLAYBACK PATH..................................................................................................................................26
FIGURE 17. STEREO BTL SPEAKER OUTPUT...............................................................................................................................29
FIGURE 18. DAC DRC FUNCTION BLOCK ..................................................................................................................................33
FIGURE 19. ADC AGC FUNCTION BLOCK..................................................................................................................................33
FIGURE 20. DRC/AGC FOR PLAYBACK/RECORDING MODE.......................................................................................................34
FIGURE 21. DRC/AGC FOR NOISE GATE MODE.........................................................................................................................35
FIGURE 22. RATIO GAIN BEHAVIOR FOR SPKVDD AND AVDD................................................................................................36
FIGURE 23. DATA TRANSFER OVER I2C CONTROL INTERFACE ...................................................................................................40
FIGURE 24. GPIO FUNCTION BLOCK ..........................................................................................................................................42
FIGURE 25. IRQ FUNCTION BLOCK.............................................................................................................................................43
FIGURE 26. JD SOURCE SELECTION ............................................................................................................................................44
FIGURE 27. POWER MANAGEMENT.............................................................................................................................................45
FIGURE 28. I2C CONTROL INTERFACE.......................................................................................................................................136
FIGURE 29. TIMING OF I2S/PCM MASTER MODE......................................................................................................................137
FIGURE 30. I2S/PCM SLAVE MODE TIMING .............................................................................................................................138
FIGURE 31. DIGITAL MICROPHONE INTERFACE TIMING............................................................................................................139
FIGURE 32. APPLICATION CIRCUIT ...........................................................................................................................................141
FIGURE 33. PACKAGE DIMENSION ............................................................................................................................................142
Multi-Channel Audio Hub/CODEC with embedded Voice
DSP and SounzRealTM Digital Sound Effect
xii
Rev. 0.93
REALTEK [ Realtek Semiconductor Corp. ]
