®
R8830I
RISC DSP Communication
RDC
16-BIT RISC MICROCONTROLLER
1. Features
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CPU Core
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Interrupt Controller
- RDC’s proprietary RISC architecture
- Five-stage pipeline
- The Interrupt controller with seven maskable
external interrupts and one non-maskable
external interrupt
- CPU Clock speed: 20/25/33 MHz
- Supports CPU ID
- Supports 32 PIO pins
Programmable Chip-select Logic
- Programmable chip-select logic for memory or
I/O bus cycle decoder
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Bus interface
- Multiplexed address and data bus which is
compatible with the 80C188 microprocessor
- Supports a non-multiplexed address bus A[19:0]
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Programmable Wait-state Generator
Counter/Timers
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ROM/RAM Controller and Addressing Space
- 1M-byte memory address space
- 64K-byte I/O space
- Three independent 16-bit timers and one
independent watchdog timer
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Software Compatible with the 80C186
Microprocessor
PSRAM Interface
- PSRAM (Pseudo Static RAM) interface with
auto-refresh control
Operating Voltage Range
- Core voltage: 5V ± 10%
- I/O voltage: 5V ± 10%
Compatible UART Channels
- UART speed : maximum baud rate up to
115.2Kbps
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Ambient temperature: - 40 ~ +85°C
Power Save and Power Down Mode Support
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Two Independent DMA Channels
- Supports serial ports with DMA transfers
Package Type
-100 Pin PQFP & 100 Pin LQFP
Asynchronous Serial Channels
- Supports two asynchronous serial channels
with hardware handshaking signals
Specifications subject to change without notice, contact your sales representatives for the most update information.
Page 2 of REV 1.0 Mar. 23 2007
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