®
R8810LV
RISC DSP Controller
RDC
Pin Description
Pin No.(PQFP)
Symbol
Type
Input
Description
System power: +3.3 volt power supply.
15, 21, 38, 61, 67, 92
VCC
12, 18, 41, 42, 64, 70,
89
System ground.
GND
Input
Reset input. When RST is asserted, the CPU immediately
terminate all operation, clears the internal registers & logic,
and the address transfers to the reset address FFFF0h.
Input to the oscillator amplifier.
71
Input*
RST
13
14
X1
X2
Input
Output from the inverting oscillator amplifier.
Output
Clock output A. The CLKOUTA operation is the same as
crystal input frequency (X1). CLKOUTA remains active during
reset and bus hold conditions.
Clock output B. The CLKOUTB operation is the same as
crystal input frequency (X1). CLKOUTB remains active
during reset and bus hold conditions.
16
17
CLKOUTA
CLKOUTB
Output
Output
Synchronous Serial Port Interface
Serial data enables. Active-high. These pins enable data
Output/Input transfers of the synchronous serial interface. SDEN1 for port1,
SDEN0 for port0.
1
2
SDEN1/PIO23
SDEN0/PIO22
Synchronous serial data clock. This pin provides the shift clock
Output/Input to an external device. SCLK=X1/2, 4, 8 or 16 depending on
register setting. This pin held high during the UART inactive.
3
SCLK/PIO20
Synchronous serial data. This pin provides the shift data to or
receives a serial data from an external device.
100
SDATA/PIO21
Input/Output
Asynchronous Serial Port Interface
Transmit data. This pin transmits asynchronous serial data
from the UART of the microcontroller.
Receive data. This pin receives asynchronous serial data.
98
99
TXD/PIO27
RXD
Output/Input
Input
Bus Interface
For RFSH2 feature, this pin actice low to indicate a DRAM
refresh bus cycle.
For ADEN feature, when this pin is held high on power-on
reset the address portion of the AD bus can be disabled or
enabled by DA bit in the LMCS and UMCS register during
4
Output/Input
RFSH2 / ADEN
LCS or UCS bus cycle access. The RFSH2 / ADEN with a
internal weak pull-up resister, so no external pull-up resister is
reqired. The AD bus always drives both address and data
during LCS or UCS bus cycle access, if the
RFSH2 / ADEN pin with external pull-Low resister during
reset.
Write strobe. This pin indicates that the data on the bus is to be
written into a memory or an I/O device. WR is active during
T2, T3 and Tw of any write cycle, floats during a bus hold or
reset.
5
Output
WR
Read Strobe. Active low signal which indicates that the
microcontroller is performing a memory or I/O read cycle.
6
7
Output
Output
RD
RD floats during bus hold or reset.
Address latch enable. Active high. This pin indicates that an
address output on the AD bus. Address is guaranteed to be
valid on the trailing edge of ALE. This pin is tri-stated during
ALE
RDC Semiconductor Co.
Subject to change without notice
Rev:1.4
8
RDC [ RDC SEMICONDUCTOR ]
