®
R8800
RISC DSP Communication
RDC
16-BIT RISC MICROCONTROLLER
1. Features
external interrupts and 1 non-maskable external
interrupt
l CPU Core
- RDC’s proprietary RISC architecture
- Five-stage pipeline
l Programmable Chip-select Logic
- Programmable chip-select logic for memory or I/O
bus cycle decoder
- CPU clock speed up to 40 MHz
- Supports CPU ID
- Supports 32 PIO pins
- Static & synthesizable design
l Programmable Wait-state Generator
l Bus Interface
l Counter/Timers
- A multiplexed address and data bus which is
compatible with the 80C188 microprocessor
- Supports a non-multiplexed address bus A[19:0]
- 3 independent 16-bit timers and Timer 1 can be
programmed as a watchdog timer
l Software compatible with the 80C188
l ROM/RAM Controller and Addressing Space
- 1M-byte memory address space
- 64K-byte I/O space
microprocessor
l Operating Voltage Range
- Core voltage: 5V ± 5%
- I/O voltage: 5V ± 10%
l PSRAM Interface
- PSRAM (Pseudo static RAM) interface with
auto-refresh control
l Ambient Temperature: 0 ~ +70°C
l Package Type
- 100-pin PQFP
- 100-pin LQFP
l Two Independent DMA Channels
l Asynchronous Serial Channel
- Supports one asynchronous serial channel with
one synchronous serial channel
l A Green Product
l Interrupt Controller
- The Interrupt controller with five maskable
Specifications subject to change without notice, contact your sales representatives for the most update information.
Page 2 of REV 1.0 Oct.26 2006
5