®
R2010
RISC DSP Communication
RDC
FAST ETHERNET RISC PROCESSOR
1. Features
l
l
l
Five-stage pipeline
l
l
Three independent 16-bit timers and one independent
programmable watchdog timer
RISC architecture
Bus interface
The Interrupt controller with five maskable
external interrupts
- Multiplexed address and Data bus
- Supports non-multiplexed address bus A [20:0]
- 16-bit external bus dynamic access
- 16M-byte memory address space
- 64K-byte I/O space
l
l
Two independent DMA channels
Programmable chip-select logic for Memory
or I/O bus cycle decoder
l
l
l
l
l
Programmable wait-state generator
With 8-bit or 16-bit Boot ROM bus size
1-Port Fast Ethernet MAC with MII interface
Supports an 8K-byte Uniform cache
With 25MHz input frequency and up to 100MHz
maximum internal frequency.
- Supports an independent data/address bus for
external I/O device
- Supports a glueless and simplified 16-bit
PCMCIA bus interface
l
Supports two compatible UART serial channels
with 16-byte FIFO and hardware flow-control.
Supports CPU ID
l
l
Compatible with 3.3V I/O and 2.5V core voltage.
Package Type includes 128-pin PQFP.
l
l
SDRAM control Interface
Specifications subject to change without notice, contact your sales representatives for the most update information.
Page 2 of REV 1.0 Nov. 28 2005
4
RDC [ RDC SEMICONDUCTOR ]
