RDC
®
RISC DSP Communication
R1621
FAST ETHERNET RISC PROCESSOR
1.
Features
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CPU Core
-
RDC's proprietary RISC architecture
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Five-stage pipeline
-
Operation frequency: 100MHz
-
Supports an 8K-byte uniform cache
-
Supports CPU ID
-
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Supports 40 PIO pins
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Fast Ethernet MAC Ports
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2-port Fast Ethernet MAC with MII interface
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The MAC packet buffer is cacheable with
snooping function
Interrupt Controller
-
The interrupt controller with five maskable
external interrupts
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Programmable Chip-select Logic
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Programmable chip-select logic for memory or
I/O bus cycle decoder
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PCMCIA Bus Interface
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Supports a glueless and simplified 16-bit
PCMCIA bus interface
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ROM/RAM/SDRAM Controller and Addressing
Space
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Supports 16-bit data bus [15:0]
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1M-byte memory address space Address[19:0]
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SDRAM control interface
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64K-byte I/O space
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Compatible UART Channels
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Supports two compatible UART serial channels
with 16-byte FIFOs and hardware flow-control
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Operating Voltage Range
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Core voltage: 2.5V
±
5%
-
I/O voltage: 3.3V
±
10%
Package Type
128-pin PQFP
Counter/Timers
-
Three independent 16-bit timers and one
independent programmable watchdog timer
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Programmable Wait-state Generators
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Two independent DMA channels
Bus Interface
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Supports non-multiplexed address bus A[19:0]
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With 8-bit or 16-bit boot ROM bus size
-
Supports an independent data/address bus for
external I/O devices
-
8-bit or 16-bit external bus dynamic access
Specifications subject to change without notice, contact your sales representatives for the most update information.
Page
2 of
4
REV
1.0
Aug. 18
2005
RDC [ RDC SEMICONDUCTOR ]
