RDC
®
RISC DSP Communication
R1620
FAST ETHERNET RISC PROCESSOR
1.
Features
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Five-stage pipeline
RISC architecture
Bus interface
- Multiplexed address and Data bus
- Supports non-multiplexed address bus A[19:0]
- 8-bit or 16-bit external bus dynamic access
- 1M-byte memory address space
- 64K-byte I/O space
- Supports an independent bus for slower I/O
device
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Software is compatible with the 80C186
microprocessor
Supports two 16550 UART serial channel with 16
bytes FIFO.
Supports CPU ID
Supports 32 PIO pins
SDRAM control Interface
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Three independent 16-bit timers and one independent
programmable watchdog timer
The Interrupt controller with six maskable external
interrupts and two non-maskable external
interrupt
Two independent DMA channels
Programmable chip-select logic for Memory or
I/O bus cycle decoder
Programmable wait-state generator
With 8-bit or 16-bit Boot ROM bus size
2-Port Fast Ethernet MAC with MII interface
With 25MHz input frequency and up to 4x25MHz
maximum internal frequency.
Compatible with 3.3V I/O.
Package Types include 160-pin PQFP and 160-pin
LQFP.
Specifications subject to change without notice, contact your sales representatives for the most update information.
Page
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5
REV
1.0
Sep. 20
2006
RDC [ RDC SEMICONDUCTOR ]
