MIL-M-38510/112B
NOTES:
1
2
3
Test circuit pin conditions shall be as specified in the schedule of this figure.
Subgroups, test temperatures and limits shall be as specified in table III.
As required to prevent oscillations. Also, proper wiring procedures shall be followed to prevent oscillations.
Loop response and settling time shall be consistent with test rate such that any value has settled to within
5% of its final value before measuring. Suggested values shown may not ensure loop stability for all
layouts. Actual compensation also shall be approved by preparing activity prior to use.
4
Precautions shall be taken to prevent damage to the D.U.T. during insertion into the socket and change of
relay contacts.
5
6
Any oscillation greater than 300 mV (pk-pk) shall be cause for device failure.
Relays K1 thru K4 select the comparator under test. The idle comparators have 1 V applied to the (-) input
to force their outputs to the low state.
7
8
9
These resistors are ±0.1% tolerance matched to ±0.01%. All other resistors are ±1% tolerance and
capacitors are 10% tolerance.
Common mode rejection is calculated using the offset voltage values measured at the common mode
range end points.
The relays shown indicate test connections only. All relays are shown in their de-energized states. Relay
coils are not shown.
10 Saturation of the nulling amplifier is not allowed on tests where E value is measured.
FIGURE 2. Test circuit for static and dynamic tests – Continued.
12
RAYTHEON [ RAYTHEON COMPANY ]
