TABLE III. Pin descriptions.
Pin
VDD, GND
X7-0
Description
The devices operate from a single +5.0 V supply. All power and ground lines must be connected.
Devices 01, 02, 05, and 06 have two 8-bit two’s complement data inputs labeled X and Y.
Y7-0
Devices 03, 04, 07, and 08 have two 8-bit unsigned magnitude data inputs labeled X and Y. The
most significant bits (MSB’s) X7 and Y7, carry the sign information for the two’s complement
notation in devices 01, 02, 05, and 06. The remaining bits are X6-0 and Y6-0 with X0 and Y0 the
LSB’s. The input and output formats for fractional and integer two’s complement, and fractional
and integer unsigned magnitude notations are shown on figure 2.
P15-0
Devices 01, 02, 05, and 06 have a 16-bit two’s complement output which is the product of the two
input X and Y values. Devices 03, 04, 07, and 08 have a 16-bit unsigned magnitude output which
is the product of the two input X and Y values. This output is divided into two 8-bit output words,
the MSP and LSP. The MSB of both the MSP and LSP is the sign bit in devices 01, 02, 05,
and06. The input and output formats for fractional and integer two’s complement, and fractional
and integer unsigned magnitude notations are shown on figure 2. Note that since +1 cannot be
exactly represented in fractional two’s complement notation, some provision for handling the case
(-1)∗(-1) must be made. Devices 01, 02, 05, and 06 output a –1 in this case. As a result, external
error handling provisions may be required.
CLK X,
CLK Y,
CLK P
These devices have three clock lines, one for each input register (CLK X and CLK Y) and one for
the product register (CLK P). Data present at the inputs of these registers are loaded into the
registers on the rising edge of the appropriate clock. In devices 01, 02, 05, and 06, the RND input
is registered and clocked in on the rising edge of the logical OR of both CLK X and CLK Y.
Special attention to the clock signals is required if normally high clock signals are used. Problems
with loading this control signal can be avoided by the use of normally low clocks. In devices 03,
04, 07, and 08, the RND input is registered and clocked in on the rising edge of CLK X.
TRIM, TRIL
RND
TRIM and TRIL are the three-state enable lines for the MSP and LSP. The output driver is in the
high impedance state when TRIM or TRIL is high, and enabled when low. TRIM and TRIL are not
registered.
When RND (round) is high, one is added to the MSB of the LSP. A one will be added to the P6 bit
in devices 01, 02, 05, and 06, or the P7 bit in devices 03, 04, 07, and 08. Note that rounding
always occurs in the positive direction. In some applications, this may introduce a systematic
bias. The RND input is registered and used when a rounded 8-bit product is desired.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88739
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
G
SHEET
15
DSCC FORM 2234
APR 97
RAYTHEON [ RAYTHEON COMPANY ]
