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VRS51L1050-25-LG-ISPV3 参数 Datasheet PDF下载

VRS51L1050-25-LG-ISPV3图片预览
型号: VRS51L1050-25-LG-ISPV3
PDF下载: 下载PDF文件 查看货源
内容描述: 的Versa 8051 MCU的3.3V与IAP / ISP功能的Flash 64KB [Versa 8051 3.3V MCU with 64KB of IAP/ISP Flash]
分类和应用:
文件页数/大小: 49 页 / 505 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
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VRS51L1050
Instruction Set
Mnemonic
Description
Size
(bytes)
1
2
1
2
1
2
2
2
2
2
2
2
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
2
3
1
1
2
3
2
2
2
3
3
3
1
2
2
3
3
3
3
2
3
1
Instr. Cycles
The following table describes the instruction set of the
VRS51L1050. The instructions are function and binary code
compatible with industry standard 8051s.
T
ABLE
3: L
EGEND FOR
I
NSTRUCTION
S
ET
T
ABLE
Symbol
A
Rn
Direct
@Ri
rel
bit
#data
#data 16
addr 16
addr 11
Function
Accumulator
Register R0-R7
Internal register address
Internal register pointed to by R0 or R1 (except MOVX)
Two's complement offset byte
Direct bit address
8-bit constant
16-bit constant
16-bit destination address
11-bit destination address
T
ABLE
4: VRS51L1050 I
NSTRUCTION
S
ET
Mnemonic
Description
Size
(bytes)
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
Instr. Cycles
Arithmetic instructions
Add register to A
ADD A, Rn
Add direct byte to A
ADD A, direct
Add data memory to A
ADD A, @Ri
Add immediate to A
ADD A, #data
Add register to A with carry
ADDC A, Rn
Add direct byte to A with carry
ADDC A, direct
Add data memory to A with carry
ADDC A, @Ri
Add immediate to A with carry
ADDC A, #data
Subtract register from A with borrow
SUBB A, Rn
Subtract direct byte from A with borrow
SUBB A, direct
Subtract data mem from A with borrow
SUBB A, @Ri
Subtract immediate from A with borrow
SUBB A, #data
Increment A
INC A
Increment register
INC Rn
Increment direct byte
INC direct
Increment data memory
INC @Ri
Decrement A
DEC A
Decrement register
DEC Rn
Decrement direct byte
DEC direct
Decrement data memory
DEC @Ri
Increment data pointer
INC DPTR
Multiply A by B
MUL AB
Divide A by B
DIV AB
Decimal adjust A
DA A
Logical Instructions
AND register to A
ANL A, Rn
AND direct byte to A
ANL A, direct
AND data memory to A
ANL A, @Ri
AND immediate to A
ANL A, #data
AND A to direct byte
ANL direct, A
AND immediate data to direct byte
ANL direct, #data
OR register to A
ORL A, Rn
OR direct byte to A
ORL A, direct
OR data memory to A
ORL A, @Ri
OR immediate to A
ORL A, #data
OR A to direct byte
ORL direct, A
OR immediate data to direct byte
ORL direct, #data
Exclusive-OR register to A
XRL A, Rn
Exclusive-OR direct byte to A
XRL A, direct
Exclusive-OR data memory to A
XRL A, @Ri
Exclusive-OR immediate to A
XRL A, #data
Exclusive-OR A to direct byte
XRL direct, A
Exclusive-OR immediate to direct byte
XRL direct, #data
Clear A
CLR A
Compliment A
CPL A
Swap nibbles of A
SWAP A
Rotate A left
RL A
Rotate A left through carry
RLC A
Rotate A right
RR A
Rotate A right through carry
RRC A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
Boolean Instruction
Clear Carry bit
CLR C
Clear bit
CLR bit
Set Carry bit to 1
SETB C
Set bit to 1
SETB bit
Complement Carry bit
CPL C
Complement bit
CPL bit
Logical AND between Carry and bit
ANL C,bit
Logical AND between Carry and not bit
ANL C,#bit
Logical ORL between Carry and bit
ORL C,bit
Logical ORL between Carry and not bit
ORL C,#bit
Copy bit value into Carry
MOV C,bit
Copy Carry value into Bit
MOV bit,C
Data Transfer Instructions
Move register to A
MOV A, Rn
Move direct byte to A
MOV A, direct
Move data memory to A
MOV A, @Ri
Move immediate to A
MOV A, #data
Move A to register
MOV Rn, A
Move direct byte to register
MOV Rn, direct
Move immediate to register
MOV Rn, #data
Move A to direct byte
MOV direct, A
Move register to direct byte
MOV direct, Rn
Move direct byte to direct byte
MOV direct, direct
Move data memory to direct byte
MOV direct, @Ri
Move immediate to direct byte
MOV direct, #data
Move A to data memory
MOV @Ri, A
Move direct byte to data memory
MOV @Ri, direct
Move immediate to data memory
MOV @Ri, #data
Move immediate to data pointer
MOV DPTR, #data
MOVC A, @A+DPTR
1
1
1
1
1
1
2
2
2
2
1
2
1
1
1
1
1
2
1
1
2
2
2
2
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
Move code byte relative DPTR to A
Move code byte relative PC to A
MOVC A, @A+PC
Move external data (A8) to A
MOVX A, @Ri
Move external data (A16) to A
MOVX A, @DPTR
Move A to external data (A8)
MOVX @Ri, A
Move A to external data (A16)
MOVX @DPTR, A
Push direct byte onto stack
PUSH direct
Pop direct byte from stack
POP direct
Exchange A and register
XCH A, Rn
Exchange A and direct byte
XCH A, direct
Exchange A and data memory
XCH A, @Ri
Exchange A and data memory nibble
XCHD A, @Ri
Branching Instructions
Absolute call to subroutine
ACALL addr 11
Long call to subroutine
LCALL addr 16
Return from subroutine
RET
Return from interrupt
RETI
Absolute jump unconditional
AJMP addr 11
Long jump unconditional
LJMP addr 16
Short jump (relative address)
SJMP rel
Jump on carry = 1
JC rel
Jump on carry = 0
JNC rel
Jump on direct bit = 1
JB bit, rel
Jump on direct bit = 0
JNB bit, rel
Jump on direct bit = 1 and clear
JBC bit, rel
Jump indirect relative DPTR
JMP @A+DPTR
Jump on accumulator = 0
JZ rel
Jump on accumulator 1= 0
JNZ rel
Compare A, direct JNE relative
CJNE A
, direct, rel
Compare A, immediate JNE relative
CJNE A, #d, rel
Compare reg, immediate JNE relative
CJNE Rn, #d, rel
Compare ind, immediate JNE relative
CJNE @Ri, #d, rel
Decrement register, JNZ relative
DJNZ Rn, rel
Decrement direct byte, JNZ relative
DJNZ direct, rel
Miscellaneous Instruction
No operation
NOP
Rn:
Any of the register R0 to R7
@Ri:
Indirect addressing using Register R0 or R1
#data: immediate Data provided with Instruction
#data16: Immediate data included with instruction
bit:
address at the bit level
rel:
relative address to Program counter from +127 to –128
Addr11: 11-bit address range
Addr16: 16-bit address range
#d:
Immediate Data supplied with instruction
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