168-pin Low Profile Registered SDRAM DIMMs
256MB, 512MB, 1GB
Preliminary Data Sheet
Serial Presence Detect (SPD) for Registered SDRAM DIMMs
256MB
512MB
1GB
256MB 512MB 1GB
Byte # Description
** HEX CODE **
0
1
2
3
Number of bytes written into EEPROM
128
256
SDRAM
12
128
128
80
08
04
0C
0C
0B
0A
02
02
48
00
01
75
54
02
80
04
08
04
08
01
8F
04
06
01
01
1F
07
A0
60
00
00
14
0F
14
2D
40
20
15
08
15
08
00
12
F2
DA
80
08
04
0D
0D
0B
0A
02
02
48
00
01
75
54
02
82
04
08
04
08
01
8F
04
06
01
01
1F
07
A0
60
00
00
14
0F
14
2D
80
40
15
08
15
08
00
12
35
FD
80
08
04
0D
0D
0B
00
02
02
48
00
01
75
54
02
82
04
Total number of SPD bytes
Memory Type
256
SDRAM
256
SDRAM
Number of Row Addresses
x4 based
x8 based
x4 based
x8 based
x4 based
x8 based
13
13
12
11
13
11
-
11
4
5
Number of Column Addresses
Number of Module Banks
10
1
10
1
-
2
2
2
-
6
7
8
9
Module Data Width
x72
0
x72
0
x72
0
Module Data Width (cont'd)
Voltage Interface Levels
Cycle Time at max CAS Latency
LVTTL
7.5 ns
5.4 ns
LVTTL
7.5 ns
LVTTL
7.5 ns
5.4 ns
10 SDRAM Clock Access Time (CL=3)
11 DIMM config (non-parity, parity, ECC)
12 Refresh Rate and Type
5.4 ns
--- ECC ---
15.6 us /self
7.8 us /self
7.8 us /self
x4
13 Primary SDRAM Width
x4 based
x8 based
x4 based
x8 based
x4
x8
x4
x8
14 Error Checking Data Width
x4
x8
x4
x8
x4
04
15 Min. CAS-to-CAS Delay (tCCD)
16 Burst Lengths Supported
17 Number of Banks on SDRAM Device
18 CAS Latencies Supported
19 CS Latency
1 clk
1 clk
1 clk
01
8F
04
06
01
01
1F
07
A0
60
00
00
14
0F
14
2D
80
--- 1,2,4,8,Full Pg ---
4
2,3
0
4
2,3
0
4
2,3
0
20 Write Latency
0
0
0
21 SDRAM Module Attributes
22 SDRAM Device Attributes
--- Registered/buffered w/ PLL ---
+/-10% Vdd, Precharge All
23 Min. Clock Cycle Time at CL=2
24 Clock Access Time at CL=2 (tAC2)
25 Min. Clock Cycle Time at CL=1
26 Clock Access Time at CL=1 (tAC1)
27 Min. Row Precharge Time (tRP)
28 Min. Row-to-Row Delay (tRRD)
29 Min. RAS-to-CAS Delay (tRCD)
30 Min. RAS Pulse Width (tRAS)
31 Density of each bank on module
10 ns
6.0 ns
N/A
10 ns
6.0 ns
N/A
10 ns
6.0 ns
N/A
N/A
N/A
N/A
20 ns
15 ns
20 ns
45 ns
256MB
128MB
20 ns
15 ns
20 ns
45 ns
20 ns
15 ns
20 ns
45 ns
x4 based
x8 based
512MB
256MB
1.5 ns
0.8 ns
1.5 ns
0.8 ns
-
512MB
-
32 Cmd/Addr input set-up time
33 Cmd/Addr input hold time
34 Data input set-up time
35 Data input hold time
36-61 Superset Information
62 SPD Rev.
15
08
15
08
00
12
36
1.2
63 Checksum for bytes 0-62
x4 based
x8 based
64-71 JEDEC ID code
Enhanced Memory Systems
7F32FFFFFFFFFFFF
72 Manufacturing Location
73-90 Manufacturer's Part #
xx
xx
xx
xx
xx
xx
xx
xx
x4 based SM25609ARDT4
x8 based SM25609ARDT8
SM51209BRDT4
SM51209BRDT8
SM1K09BRDT4
91,92 PCB Rev. Code
93,94 Manufacturing Date
rrrr
yyww
ssss
00
rrrr
yyww
ssss
00
rrrr
yyww
ssss
00
yyww code
serial number
open
95-98 Assembly Serial #
99-125 Manufacturer's Specific Data
126 Intel specification frequency
127 Intel specification CL and clock support
128-255 Open for Customer Use
100MHz
64
64
64
87
00
87
00
87
00
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 12
Revision 1.1
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
