Preliminary Data Sheet
Industrial Temperature
16Mbit Enhanced Synchronous DRAM
1Mx16 ESDRAM
Description
As a JEDEC superset standard, the Enhanced Synchronous
DRAM (ESDRAM) is an evolutionary modification to the
JEDEC standard SDRAM. The industrial temperature grade
version operates over an extended temperature range of -40°C
to 85
°C.
While completely compatible with standard
SDRAM, ESDRAM incorporates changes that reduce
latency, increase bandwidth, and allow concurrent operations
to the same bank.
The 16Mbit ESDRAM combines a fast DRAM array with an
8Kbit SRAM cache. The DRAM array is separated into two
fully independent 8Mbit banks, with 4Kbits of SRAM cache
per bank. The cache provides high-speed random column
access, and with auto-precharge, allows operations to the
DRAM array concurrent with cache reads. These operations
include row activation, precharge, and refresh. Hidden row
activation makes it possible to pipeline random row reads to
reduce the page miss latency to that of a page hit.
This device supports Self Refresh mode and operates with a
single 3.3V
±
0.3V power supply. It is available in a 400mil
TSOP Type II package.
Features
•
•
Extended Temperature Range (-40°C to 85
°C)
High Performance:
CAS Latency = 2
f
CK
t
CK2
t
AC2
Clock Frequency
Clock cycle
Clock Access Time
-7.5
133
7.5
4.5
-10
100
10
5
Units
MHz
ns
ns
•
•
•
•
•
•
•
•
•
•
•
JEDEC Superset Standard ESDRAM
8Kbit SRAM Row Cache
Supports Row Pipelining for Random Row Reads
Programmable Burst length (1, 2, 4, 8, full page)
Programmable CAS Latency (1, 2, 3)
Automatic and Controlled Precharge Command
Low Power Suspend, Self Refresh, and Power
Down Modes Supported
2K Refresh / 64 ms
Single 3.3V
±
0.3V Power Supply
LVTTL and 2.5V I/O Interface with Flexible V
DDQ
50-pin TSOP-II (0.8mm pin pitch)
1Mx16 ESDRAM Block Diagram
Address Buffers
Row Decoder
A(11:0)
Bank A
8Mbit
Bank B
8Mbit
Data Latches
Sense Amplifiers
Sense Amplifiers
CLK
CKE
/CS
/RAS
/CAS
/WE
UDQM
LDQM
Command
Decoder
and
Timing
Generator
SRAM Row Cache
Column Decoder
SRAM Row Cache
Column Decoder
Data I/O Buffers
DQ
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
1999 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Data Latches
Page 1 of 9
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
