FM33256/FM3316 SPI Companion w/ FRAM
Setting
2.60V
2.75V
2.9V
VTP(1:0)
00 (factory default)
01
10
11
3.0V
17h
16h
15h
14h
13h
12h
11h
10h
Serial Number Byte 7
D7
D6
D5
D4
D3
D2
D1
D0
SN.63
SN.62
SN.61
SN.60
SN.59
SN.58
SN.57
SN.56
Serial Number Byte 6
D7
D6
D5
D4
D3
D2
D1
D0
SN.55
SN.54
SN.53
SN.52
SN.51
SN.50
SN.49
SN.48
Serial Number Byte 5
D7
D6
D5
D4
D3
D2
D1
D0
SN.47
SN.46
SN.45
SN.44
SN.43
SN.42
SN.41
SN.40
Serial Number Byte 4
D7
D6
D5
D4
D3
D2
D1
D0
SN.39
SN.38
SN.37
SN.36
SN.35
SN.34
SN.33
SN.32
Serial Number Byte 3
D7
D6
D5
D4
D3
D2
D1
D0
SN.31
SN.30
SN.29
SN.28
SN.27
SN.26
SN.25
SN.24
Serial Number Byte 2
D7
D6
D5
D4
D3
D2
D1
D0
SN.23
SN.22
SN.21
SN.20
SN.19
SN.18
SN.17
SN.16
Serial Number Byte 1
D7
D6
D5
D4
D3
D2
D1
D0
SN.15
SN.14
SN.13
SN.12
SN.11
SN.10
SN.9
SN.8
Serial Number Byte 0
D7
D6
D5
D4
D3
D2
D1
D0
SN.7
SN.6
SN.5
SN.4
SN.3
SN.2
SN.1
SN.0
All serial number bytes are read/write when SNL=0, read-only when SNL=1. Nonvolatile.
0Fh
0Eh
Event Counter Byte 1
D7
D6
D5
D4
D3
D2
D1
D0
EC.15
EC.14
EC.13
EC.12
EC.11
EC.10
EC.9
EC.8
Event Counter Byte 1. Increments on programmed edge event on CNT input. Nonvolatile when NVC=1,
Battery-backed when NVC=0, read/write.
Event Counter Byte 0
D7
D6
D5
D4
D3
D2
D1
D0
EC.7
EC.6
EC.5
EC.4
EC.3
EC.2
EC.1
EC.0
Event Counter Byte 0. Increments on programmed edge event on CNT input. Nonvolatile when NVC=1,
Battery-backed when NVC=0, read/write.
0Dh
Event Counter Control
D7
D6
D5
D4
D3
D2
D1
D0
NVC
-
-
-
RC
WC
POLL
CP
NVC
Nonvolatile/Volatile Counter: Setting this bit to 1 makes the counter nonvolatile and counter operates only when
VDD is greater than VTP. Setting this bit to 0 makes the counter volatile, which allows counter operation under
VBAK or VDD power. Nonvolatile, read/write.
RC
Read Counter. Setting this bit to 1 takes a snapshot of the two counter bytes allowing the system to read the
values without missing count events. The RC bit will be automatically cleared.
WC
Write Counter. Setting this bit to a 1 allows the user to write the counter bytes. While WC=1, the counter is
blocked from count events on the CNT pin. The WC bit must be cleared by the user to activate the counter.
Polled Mode: When POLL=1, the CNT pin is sampled for 30µs every 125ms. If POLL is set, the NVC bit is
internally cleared and the CP bit is set to detect a rising edge. The RTC oscillator must be enabled (/OSCEN=0)
POLL
Rev. 1.0
Dec. 2006
Page 14 of 28
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
