欢迎访问ic37.com |
会员登录 免费注册
发布采购

FM32L274-G 参数 Datasheet PDF下载

FM32L274-G图片预览
型号: FM32L274-G
PDF下载: 下载PDF文件 查看货源
内容描述: 3V集成处理器伴侣与记忆 [3V Integrated Processor Companion with Memory]
分类和应用:
文件页数/大小: 21 页 / 275 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
 浏览型号FM32L274-G的Datasheet PDF文件第1页浏览型号FM32L274-G的Datasheet PDF文件第2页浏览型号FM32L274-G的Datasheet PDF文件第3页浏览型号FM32L274-G的Datasheet PDF文件第4页浏览型号FM32L274-G的Datasheet PDF文件第6页浏览型号FM32L274-G的Datasheet PDF文件第7页浏览型号FM32L274-G的Datasheet PDF文件第8页浏览型号FM32L274-G的Datasheet PDF文件第9页  
FM32L278/L276/L274/L272 - 3V I2C Companion  
Manual Reset  
The bit VTP controls the trip point of the low voltage  
detect circuit. It is located in register 0Bh, bit 0. Note  
that the bit 1 location is a “don’t care”.  
The /RST pin is bi-directional and allows the  
FM32L27x to filter and de-bounce a manual reset  
switch. The /RST input detects an external low  
condition and responds by driving the /RST signal  
low for 100 ms.  
VTP  
VTP  
2.6V  
2.9V  
0
1
MCU  
RST  
FM32L27x  
The watchdog timer can also be used to assert the  
reset signal (/RST). The watchdog is a free running  
programmable timer. The period can be software  
programmed from 100 ms to 3 seconds in 100 ms  
increments via a 5-bit nonvolatile register. All  
programmed settings are minimum values and vary  
with temperature according to the operating  
specifications. The watchdog has two additional  
controls associated with its operation, a watchdog  
enable bit (WDE) and timer restart bits (WR). Both  
the enable bit must be set and the watchdog must  
timeout in order to drive /RST active. If a reset event  
occurs, the timer will automatically restart on the  
rising edge of the reset pulse. If WDE=0, the  
watchdog timer runs but a watchdog fault will not  
cause /RST to be asserted low. The WTR flag will be  
set, indicating a watchdog fault. This setting is useful  
during software development and the developer does  
not want /RST to drive. Note that setting the  
maximum timeout setting (11111b) disables the  
counter to save power. The second control is a nibble  
that restarts the timer preventing a reset. The timer  
should be restarted after changing the timeout value.  
Reset  
Switch  
Switch  
Behavior  
FM32L27x  
drives  
RST  
100 ms (min.)  
Figure 4. Manual Reset  
Note that an internal weak pull-up on /RST  
eliminates the need for additional external  
components.  
Reset Flags  
In case of a reset condition, a flag will be set to  
indicate the source of the reset. A low VDD reset or  
manual reset is indicated by the POR flag, register  
09h bit 6. A watchdog reset is indicated by the WTR  
flag, register 09h bit 7. Note that the flags are  
internally set in response to reset sources, but they  
must be cleared by the user. When the register is  
read, it is possible that both flags are set if both have  
occurred since the user last cleared them.  
The watchdog timeout value is located in register  
0Ah, bits 4-0, and the watchdog enable is bit 7. The  
watchdog is restarted by writing the pattern 1010b to  
the lower nibble of register 09h. Writing this pattern  
will also cause the timer to load new timeout values.  
Writing other patterns to this address will not affect  
its operation. Note the watchdog timer is free-  
running. Prior to enabling it, users should restart the  
timer as described above. This assures that the full  
timeout period will be set immediately after enabling.  
The watchdog is disabled when VDD is below VTP.  
The following table summarizes the watchdog bits.  
Early Power Fail Comparator  
An early power fail warning can be provided to the  
processor well before VDD drops out of spec. The  
comparator is used to create a power fail interrupt  
(NMI). This can be accomplished by connecting the  
PFI pin to the unregulated power supply via a resistor  
divider. An application circuit is shown below.  
VDD  
Regulator  
Watchdog timeout  
Watchdog enable  
Watchdog restart  
WDT4-0 0Ah, bits 4-0  
WDE  
0Ah, bit 7  
WR3-0  
09h, bits 3-0  
FM32L27x  
WR3-0 = 1010b to restart  
Counter  
100 ms  
clock  
Timebase  
PFI  
/RST  
+
To MCU  
PFO  
NMI input  
-
1.2V ref  
Watchdog  
timeout  
WDE  
Figure 5. Comparator as Early Power-Fail Warning  
Figure 3. Watchdog Timer  
Rev. 3.0  
Feb. 2009  
Page 5 of 21  
 复制成功!