FM25L256 Extended Temp.
CS
0
SCK
1
2
3
4
5
6
7
SI
SO
0
0
0
0
Hi-Z
0
1
0
0
Figure 6. WRDI Bus Configuration
RDSR - Read Status Register
The RDSR command allows the bus master to verify
the contents of the Status register. Reading Status
provides information about the current state of the
write protection features. Following the RDSR op-
code, the FM25L256 will return one byte with the
contents of the Status register. The Status register is
described in detail in a later section.
Status Register & Write Protection
The write protection features of the FM25L256 are
multi-tiered. Taking the /WP pin to a logic low state
is the hardware write protect function. All write
operations are blocked when /WP is low. To write the
memory with /WP high, a WREN op-code must first
be issued. Assuming that writes are enabled using
WREN and by /WP, writes to memory are controlled
by the Status register. As described above, writes to
the status register are performed using the WRSR
command and subject to the /WP pin. The Status
register is organized as follows.
Rev. 2.3
March 2007
D
E
D S
N N
E G
M SI
6B
M E
25
O D
5L
C
2
E W
: FM
R E
ve
T N
ati
O R
tern
N O
Al
F
Figure 7. RDSR Bus Configuration
Figure 8. WRSR Bus Configuration
Table 2. Status Register
Bit
Name
7
6
5
WPEN
0
0
4
3
2
1
0
BP1
BP0
WEL
WRSR – Write Status Register
The WRSR command allows the user to select
certain write protection features by writing a byte to
the Status register. Prior to issuing a WRSR
command, the /WP pin must be high or inactive.
Prior to sending the WRSR command, the user must
send a WREN command to enable writes. Note that
executing a WRSR command is a write operation
and therefore clears the Write Enable Latch.
0
0
Bits 0 and 4-6 are fixed at 0 and cannot be modified.
Note that bit 0 (Ready in EEPROMs) is unnecessary
as the FRAM writes in real-time and is never busy.
The BP1 and BP0 control software write protection
features. They are nonvolatile (shaded yellow). The
WEL flag indicates the state of the Write Enable
Latch. Attempting to directly write the WEL bit in
the status register has no effect on its state. This bit
Page 6 of 14
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