FM25640
CS
0
SCK
op-code
SI
SO
0
0
0
0
0
0
1
0
X
MSB
X
X
13-bit Address
12 11 10
Data
5 4
1
2
3
4
5
6
7
0
1
2
3
4
5
3
4
5
6
7
0
1
2
3
4
5
6
7
4
3
2
1
0
7
6
3
2
1
0
LSB
LSB MSB
Figure 9. Memory Write
CS
0
SCK
op-code
SI
0
0
0
0
0
0
1
1
X
MSB
SO
X
13-bit Address
X 12 11 10
4
3
2
1
0
LSB MSB
7
6
5
Data
4 3
2
1
LSB
0
1
2
3
4
5
6
7
0
1
2
3
4
5
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 10. Memory Read
be located within the same row. In the FM25640,
there are 2048 rows each 32 bits wide. Each 4 bytes
in the address mark the beginning of a new row.
Regardless, FRAM read and write endurance is
effectively unlimited at the 5MHz clock speed. Even
at 2000 accesses per second to the same row, 15
years time will elapse before 10
12
endurance cycles
occur.
Endurance
Internally, a FRAM operates with a read and restore
mechanism similar to a DRAM. Therefore,
endurance cycles are applied for each access: read or
write. The FRAM architecture is based on an array of
rows and columns. Each access causes a cycle for an
entire row. Therefore, data locations targeted for
substantially differing numbers of cycles should not
Rev. 3.0
Mar. 2005
8 of 13
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
