FM25040A
CS
0
SCK
op-code
SI
SO
0
0
0
0
A
0
1
0
7
MSB
Hi-Z
6
Byte Address
5 4 3 2
Data
4 3
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
7
1
0
7
6
5
2
1
0
LSB
0
LSB MSB
Figure 9. Memory Write
CS
0
SCK
op-code
SI
SO
0
0
0
0
A
0
1
1
7
MSB
Hi-Z
Byte Address
6 5 4 3 2
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
7
1
0
LSB
7 6
MSB
5
Data Out
4 3 2
1
0
LSB
0
LSB
Figure 10. Memory Read
Endurance
Internally, a FRAM operates with a read and restore
mechanism similar to a DRAM. Therefore,
endurance cycles are applied for each access: read or
write. The FRAM architecture is based on an array of
rows and columns. Each access causes an endurance
cycle for an entire row. Therefore, data locations
targeted for substantially differing numbers of cycles
should not be located within the same row. In the
FM25040A, there are 128 rows each 32 bits wide.
Regardless, FRAM read and write endurance is
effectively unlimited at the 20 MHz clock speed.
Even at 2000 accesses per second to the same row, 15
years time will elapse before 10
12
endurance cycles
occur.
Rev. 3.0
May 2006
Page 8 of
13
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
